Stephen Boyd writes:
> On 08/22, Neil Armstrong wrote:
>> Add the PWM related clocks in order to be referenced as PWM source
>> clocks.
>>
>> Signed-off-by: Neil Armstrong
>> ---
>
> Acked-by: Stephen Boyd
>
> With some more thought, it should go through whatever tree takes
> the dts changes.
* Arnd Bergmann [160906 06:20]:
> When CONFIG_PM_SLEEP is disabled, we get a build error in
> the cppi41 dmaengine driver, since the runtime-pm functions
> are hidden within the wrong #ifdef:
>
> drivers/dma/cppi41.c:1158:21: error: 'cppi41_runtime_suspend' undeclared here
> (not in a function)
Hi,
On Wed, Sep 07, 2016 at 09:41:19PM +0200, Linus Walleij wrote:
> On Wed, Aug 31, 2016 at 10:25 AM, Milo Kim wrote:
>
> > H3 has single PWM channel. The second PWM channel is not supported,
> > so the pinctrl function should be removed.
> >
> > Cc: Linus Walleij
> > Cc: Maxime Ripard
> > Cc
On Wed, Aug 31, 2016 at 2:30 PM, Vincent Stehlé
wrote:
> In function mrfld_pinctrl_probe(), when duplicating the mrfld_families
> array the requested memory region length is multiplied once too many by the
> number of elements in the original array. Fix this to spare some memory.
>
> Fixes: 4e80c
From: Joshua Frkuska
This reparents the adapter created in i2c-mux to this module for
module unloading and chaining purposes.
Signed-off-by: Joshua Frkuska
Signed-off-by: Jim Baxter
---
drivers/i2c/muxes/i2c-mux-gpio.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/d
Daniel Baluta writes:
> On Tue, Dec 8, 2015 at 4:35 PM, Daniel Baluta wrote:
>> Running lguest without arguments or with a wrong argument name
>> borks the terminal, because the cleanup handler is set up too late
>> in the initialization process.
>>
>> Signed-off-by: Daniel Baluta
>
> Hi Rusty,
Hi Keith,
I like this. I think this fits into pciehp pretty well. Minor
comments below.
On Fri, Aug 26, 2016 at 11:23:01AM -0600, Keith Busch wrote:
> This patch adds a new flag to the pci_dev structure instructing pciehp to
> ignore PCIe slot LED indicators. The pciehp driver will instead prov
From: Joshua Frkuska
This new api allows the i2c adapter created by i2c-mux to be owned by
the module that calls this api. This allows module removal chaining to
be done at a higher level.
Signed-off-by: Joshua Frkuska
Signed-off-by: Jim Baxter
---
drivers/i2c/i2c-mux.c | 14 --
From: Jim Baxter
This patchset adds a new i2c_mux_add_reparented_adapter API to the i2c
that allows owning modules to use module_get/module_put and stop the
i2c bus module being removed whilst in use.
This was tested on an ARM i.MX6 Sabre board with the pca953x gpio module.
Joshua Frkuska (2):
On Wed, Aug 31, 2016 at 2:24 PM, Lee Jones wrote:
> The following changes since commit 694d0d0bb2030d2e36df73e2d23d5770511dbc8d:
>
> Linux 4.8-rc2 (2016-08-14 19:11:36 -0700)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git
> ib-mfd-gp
On Thu, Sep 1, 2016 at 9:23 AM, Krzysztof Kozlowski
wrote:
> Patch #1 should probably go through pinctrl tree. In that case I would
> appreciate a stable branch/tag so DTS could base on top of it.
I don't see why. I have no changes in this area in the pinctrl tree
for v4.9, so take it all throug
Neil Armstrong writes:
> Signed-off-by: Neil Armstrong
> ---
> arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 9 +
> 1 file changed, 9 insertions(+)
Applied,
Kevin
> diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
> b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
> index e502c
Neil Armstrong writes:
> Add support for the PWM controller found in Amlogic Meson SoCs.
> This controller provides a dual PWM output with 4 selectable clock source
> and a two level divider to achieve a better PWM range.
>
> Currently Meson8b and GXBB SoCs are supported.
>
> Changes since v2 at
Hi Vadim,
Thanks for the update. Please refer to my comments in the code.
On 09/07/2016 06:42 PM, vad...@mellanox.com wrote:
From: Vadim Pasternak
This makes it possible to create a set of LEDs for Mellanox systems:
"msx6710", "msx6720", "msb7700", "msn2700", "msx1410", "msn2410",
"msb7800",
I have one comment though, if you're anyway making changes to all
the DTS files:
On Thu, Sep 1, 2016 at 9:23 AM, Krzysztof Kozlowski
wrote:
> - samsung,pin-function = <2>;
> - samsung,pin-pud = <0>;
> - samsung,pin-drv = <0>;
> + samsung,pi
Hi Vadim,
Please just include these changes to the new version
of the patch.
On 09/07/2016 04:53 PM, vad...@mellanox.com wrote:
From: Vadim Pasternak
Fix in comments 3KHz and 6KHz to 3Hz and 6Hz respectively.
Signed-off-by: Vadim Pasternak
---
drivers/leds/leds-mlxcpld.c | 10 +-
1
On 7 September 2016 at 19:17, Linus Torvalds
wrote:
> On Wed, Sep 7, 2016 at 10:06 AM, Kees Cook wrote:
>>
>> +#ifndef CONFIG_HARDENED_USERCOPY_PAGESPAN
>> + /*
>> +* The page-spanning checks are hitting false positives, so
>> +* do not check them for now.
>> +*/
>>
On Wed, Sep 7, 2016 at 2:13 PM, dbasehore . wrote:
> On Tue, Sep 6, 2016 at 10:18 AM, Sean Paul wrote:
>> On Mon, Sep 5, 2016 at 1:06 AM, Lin Huang wrote:
>>> when in ddr frequency scaling process, vop can not do enable or
>>> disable operation, since in dcf we check vop clock to see whether
>>>
On Thu, Sep 1, 2016 at 8:42 PM, Julia Lawall wrote:
> Check for pinctrl_ops and pinmux_ops structures that are only stored in the
> pctlops field and the pmxops field, respectively, of a pinctrl_desc
> structure. These fields are declared const, so pinctrl_ops and pinmux_ops
> structures that ha
On Thu, Sep 1, 2016 at 8:42 PM, Julia Lawall wrote:
> Check for pinctrl_ops and pinmux_ops structures that are only stored in the
> pctlops field and the pmxops field, respectively, of a pinctrl_desc
> structure. These fields are declared const, so pinctrl_ops and pinmux_ops
> structures that ha
On Thu, Sep 1, 2016 at 8:42 PM, Julia Lawall wrote:
> Check for pinctrl_ops and pinmux_ops structures that are only stored in the
> pctlops field and the pmxops field, respectively, of a pinctrl_desc
> structure. These fields are declared const, so pinctrl_ops and pinmux_ops
> structures that ha
On 2016-09-07 11:53, Mark Brown wrote:
> On Tue, Sep 06, 2016 at 11:01:15AM -0700, Stefan Agner wrote:
>> On 2016-09-06 01:22, Mark Brown wrote:
>
>> > This is nonsense unless the device can work without this supply. Given
>> > that the supply is called VCC that doesn't seem entirely likely.
>
>
Hi,
On Tue, Sep 06, 2016 at 10:08:05PM +0800, Chen-Yu Tsai wrote:
> On Tue, Sep 6, 2016 at 8:18 PM, Maxime Ripard
> wrote:
> > Now that we have support for the CCU driver in sunxi-ng, convert the A23
> > and A33 DTs to that driver.
> >
> > Signed-off-by: Maxime Ripard
>
> Acked-by: Chen-Yu Tsai
Petr Mladek writes:
> The commit 66cc69e34e86a231 ("Fix: module signature vs tracepoints:
> add new TAINT_UNSIGNED_MODULE") updated module_taint_flags() to
> potentially print one more character. But it did not increase the
> size of the corresponding buffers in m_show() and print_modules().
I ag
On Tue, Sep 6, 2016 at 1:33 AM, kernel test robot wrote:
>
> FYI, we noticed the following commit:
>
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
> commit 761ed4a94582ab291aa24dcbea4e01e8936488c8 ("tty: serial_core: convert
> uart_close to use tty_port_close")
>
>
On 09/07/16 12:38, Steven Rostedt wrote:
> On Wed, 7 Sep 2016 14:48:38 -0400
> Steven Rostedt wrote:
>
>> Will send another one soon.
>
> What about this?
>
> -- Steve
>
> commit 64cfdb9788bf3fb2bf6c30701fc3644f25e76df2
> Author: Steven Rostedt (Red Hat)
> Date: Wed Sep 7 12:45:09 2016 -040
On 2016-09-05 11:00, Stefan Agner wrote:
> The cachepolicy variable gets initialized using a masked pmd
> value. So far, the pmd has been masked with flags valid for the
> 2-page table format, but the 3-page table format requires a
> different mask. On LPAE, this lead to a wrong assumption of what
On Mon, Sep 05, 2016 at 06:42:56PM +0200, Greg Kroah-Hartman wrote:
> This is the start of the stable review cycle for the 4.7.3 release.
> There are 143 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
On Tue, Sep 6, 2016 at 6:45 PM, Alexandre TORGUE
wrote:
> This patch adds IRQ support to STM32 gpios.
>
> The EXTI controller has 16 lines dedicated to GPIOs.
> EXTI line n can be connected to only line n of one of the GPIO ports, for
> example EXTI0 can be connected to either PA0, or PB0, or PC0
Hi Guenter,
On Wed, Sep 7, 2016 at 12:24 PM, Guenter Roeck wrote:
> On Wed, Sep 07, 2016 at 11:55:06AM -0700, Hoan Tran wrote:
>> Hi Guenter,
>>
>> On Tue, Sep 6, 2016 at 11:39 PM, Guenter Roeck wrote:
>> > On 09/06/2016 11:07 PM, Hoan Tran wrote:
>> >>
>> >> Hi Guenter,
>> >>
>> >> On Tue, Sep
On 2016-08-29 12:27 PM, Chris Metcalf wrote:
> On 8/16/2016 5:19 PM, Chris Metcalf wrote:
>> Here is a respin of the task-isolation patch set.
>
> No concerns have been raised yet with the v15 version of the patch series
> in the two weeks since I posted it, and I think I have addressed all
> previ
On 2016-09-07 16:49, Jani Nikula wrote:
On Tue, 06 Sep 2016, li...@eikelenboom.it wrote:
On 2016-09-06 11:25, Jani Nikula wrote:
On Tue, 06 Sep 2016, li...@eikelenboom.it wrote:
L.S.,
Since one of the last 4.8 RC's i'm getting the warning below when
booting on my sandybridge based thinkpad.
On Sun, Sep 4, 2016 at 1:04 PM, Krzysztof Kozlowski wrote:
> From: Krzysztof Kozlowski
>
> Hard-coded pinctrl configuration values are scattered through DTS files.
> The numbers are difficult to decode by human, especially without the
> datasheet. Additionally the drive strength differs between
On Sun, Sep 4, 2016 at 1:04 PM, Krzysztof Kozlowski wrote:
> From: Krzysztof Kozlowski
>
> Update examples in Samsung pinctrl dt-bindings with new macros coming
> from header file.
>
> Signed-off-by: Krzysztof Kozlowski
> Reviewed-by: Javier Martinez Canillas
Acked-by: Linus Walleij
Yours,
On Wed, Sep 07, 2016 at 01:27:35PM +0300, Yauheni Kaliuta wrote:
> The patch instrument different places of resource limits checks with
> reporting using the infrastructure from the previous patch.
>
> Signed-off-by: Yauheni Kaliuta
> ---
> arch/ia64/kernel/perfmon.c | 4 +++-
>
On Wed, Sep 07, 2016 at 09:25:59PM +0200, Jiri Olsa wrote:
> On Wed, Sep 07, 2016 at 09:58:01AM -0700, Linus Torvalds wrote:
> > On Wed, Sep 7, 2016 at 9:38 AM, Andi Kleen wrote:
> > >>
> > >> - n = copy_to_user(buffer, (char *)start,
> > >> tsz);
> > >> +
On 09/07, Neil Armstrong wrote:
> Correct prefix is MDM instead of MSM.
>
> Fixes: 8aa788d3e59a ("ARM: configs: qualcomm: Add MDM9615 missing defconfigs")
> Signed-off-by: Neil Armstrong
> ---
Reviewed-by: Stephen Boyd
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Li
On 09/07, Jerome Brunet wrote:
> SPI clock is needed for the spifc driver, expose to DT
> (and comment out in the clk driver)
>
> Signed-off-by: Jerome Brunet
> ---
Acked-by: Stephen Boyd
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Pr
On Wed, Sep 7, 2016 at 12:15 PM, Linus Torvalds
wrote:
> On Wed, Sep 7, 2016 at 11:36 AM, Kees Cook wrote:
>>
>> - move page-spanning check behind a CONFIG since it's triggering false
>> positives
>
> Hmm. I pulled this, but looking at it I realized that
>
> + depends on !COMPILE_TEST
>
>
The state of USB ChipIdea support on Qualcomm's platforms is not great.
The DT description of these devices requires up to three different nodes
for what amounts to be the same hardware block, when there should really
only be one. Furthermore, the "phy" driver that is in mainline (phy-msm-usb.c)
du
The chipidea/udc.c file sends a CI_HDRC_CONTROLLER_RESET_EVENT to
the wrapper drivers when it calls hw_device_reset(), but that
function is not called from chipidea/host.c. And the udc.c file
sends the CI_HDRC_CONTROLLER_STOPPED_EVENT but the host.c file
doesn't do anything.
The intent of the rese
We don't call hw_device_reset() with the ci->lock held, so it
doesn't seem like this lock here is protecting anything. Let's
just remove it. This allows us to call sleeping functions like
phy_init() from within the CI_HDRC_CONTROLLER_RESET_EVENT hook.
Acked-by: Peter Chen
Cc: Greg Kroah-Hartman
In the case of ULPI devices, we want to be able to load the
driver before registering the device so that we don't get stuck
in a loop waiting for the phy module to appear and failing usb
controller probe. Currently we request the ulpi module via the
ulpi ids, but in the DT case we might need to req
The MSM chipidea wrapper has two bits that are used to reset the
first or second phy. Add support for these bits via the reset
controller framework, so that phy drivers can reset their
hardware at the right time during initialization.
Acked-by: Peter Chen
Cc: Greg Kroah-Hartman
Signed-off-by: St
The ULPI phy on qcom platforms needs to be initialized and
powered on after a USB reset and before we toggle the run/stop
bit. Otherwise, the phy locks up and doesn't work properly.
Therefore, add a flag to skip any phy power management in the
core layer, leaving it up to the glue driver to manage.
The ULPI phy on qcom platforms needs to be initialized and
powered on after a USB reset and before we toggle the run/stop
bit. Otherwise, the phy locks up and doesn't work properly. Hook
the phy initialization into the RESET event and the phy power off
into the STOPPED event.
Acked-by: Peter Chen
The HSIC USB controller on qcom SoCs has an integrated all
digital phy controlled via the ULPI viewport.
Cc: Kishon Vijay Abraham I
Cc:
Signed-off-by: Stephen Boyd
---
.../devicetree/bindings/phy/qcom,usb-hsic-phy.txt | 65 +
drivers/phy/Kconfig| 7 +
The high-speed phy on qcom SoCs is controlled via the ULPI
viewport.
Cc: Kishon Vijay Abraham I
Cc:
Signed-off-by: Stephen Boyd
---
.../devicetree/bindings/phy/qcom,usb-hs-phy.txt| 83 ++
drivers/phy/Kconfig| 8 +
drivers/phy/Makefile
If something fails in ci_hdrc_add_device() due to probe defer, we
shouldn't print an error message. Be silent in this case as we'll
try probe again later.
Acked-by: Peter Chen
Cc: Greg Kroah-Hartman
Signed-off-by: Stephen Boyd
---
drivers/usb/chipidea/ci_hdrc_msm.c | 3 ++-
1 file changed, 2 i
If two devices are probed with this same driver, they'll share
the same platform data structure, while the chipidea core layer
writes and modifies it. This can lead to interesting results
especially if one device is an OTG type chipidea controller and
another is a host. Let's create a copy of this
When the RESET bit is set in the USBCMD register it resets quite
a few of the wrapper's registers to their reset state. This
includes the GENCONFIG and GENCONFIG2 registers. Currently this
is done by the usb phy and ehci-msm drivers writing into the
controller wrapper's MMIO address space. Let's co
The msm chipidea controller uses two main clks, an AHB clk to
read/write the MMIO registers and a core clk called the system
clk that drives the controller itself. Add support for these clks
as they're required in all designs.
Also add support for an optional third clk that we need to turn
on to r
We need to pick the correct phy at runtime based on how the SoC
has been wired onto the board. If the secondary phy is used, take
it out of reset and mux over to it by writing into the TCSR
register. Make sure to do this on reset too, because this
register is reset to the default value (primary phy
The MSM_USB_BASE macro trick is not very clear, and we're using
it for only one register write so let's just move to using
hw_write_id_reg() and passing the ci pointer instead. That
clearly shows what offset we're using and avoids needing to
include the msm_hsusb_hw.h file when we're going to delet
The two extcon notifiers are almost the same except for the
variable name for the cable structure and the id notifier inverts
the cable->state logic. Make it the same and replace two
functions with one to save some lines. This also makes it so that
the id cable state is true when the id pin is pull
We're not properly marking the glue layer/wrapper device as
runtime active, so runtime PM believes that the hardware state is
inactive when we call pm_runtime_enable() in this driver. This
causes a problem when the glue layer has a power domain
associated with it, because runtime PM will go and dis
The core framework already handles setting this parameter with a
platform quirk. Add the appropriate flag so that we always set
AHBBURST to 0. Technically DT should be doing this, but we always
do it for msm chipidea devices so setting the flag in the driver
works just as well. If the burst needs t
Some phys for the chipidea controller are controlled via the ULPI
viewport. Add support for the ULPI bus so that these sorts of
phys can be probed and read/written automatically without having
to duplicate the viewport logic in each phy driver.
Acked-by: Peter Chen
Cc: Greg Kroah-Hartman
Cc: Hei
On 2016-09-07 05:11 PM, Francis Giraldeau wrote:
> The syscall test fails on x86:
> $ sudo ./isolation
> [...]
> test_syscall: FAIL (0x100)
> test_syscall (SIGUSR1): FAIL (0x100)
>
> I wanted to debug this problem with gdb and a KVM virtual machine. However,
> the TSC clock source
The qcom HSIC ULPI phy doesn't have any bits set in the vendor or
product ID registers. This makes it impossible to make a ULPI
driver match against the ID registers. Add support to discover
the ULPI phys via DT help alleviate this problem. In the DT case,
we'll look for a ULPI bus node underneath
With the id and vbus detection done via extcon we need to make
sure we poll the status of OTGSC properly by considering what the
extcon is saying, and not just what the register is saying. Let's
move this hw_wait_reg() function to the only place it's used and
simplify it for polling the OTGSC regis
We're currently emulating the vbus and id interrupts in the OTGSC
read API, but we also need to make sure that if we're handling
the events with extcon that we don't enable the interrupts for
those events in the hardware. Therefore, properly emulate this
register if we're using extcon, but don't en
Hi Steven,
On Wed, 7 Sep 2016 15:38:10 -0400 Steven Rostedt wrote:
>
> commit 64cfdb9788bf3fb2bf6c30701fc3644f25e76df2
> Author: Steven Rostedt (Red Hat)
> Date: Wed Sep 7 12:45:09 2016 -0400
>
> tracing: Have max_latency be defined for HWLAT_TRACER as well
>
> The hwlat tracer u
The ULPI bus can be built as a module, and it will soon be
calling these functions when it supports probing devices from DT.
Export them so they can be used by the ULPI module.
Cc: Rob Herring
Cc:
Signed-off-by: Stephen Boyd
---
drivers/of/device.c | 2 ++
1 file changed, 2 insertions(+)
diff
On Thursday, July 21, 2016 1:55:56 PM CEST Hoan Tran wrote:
> + ctx->comm_base_addr = cppc_ss->base_address;
> + if (ctx->comm_base_addr) {
> + ctx->pcc_comm_addr =
> + acpi_os_ioremap(ctx->comm_base_addr,
> +
On Wed, Sep 7, 2016 at 2:32 PM, Kees Cook wrote:
> On Wed, Sep 7, 2016 at 12:15 PM, Linus Torvalds
> wrote:
>> On Wed, Sep 7, 2016 at 11:36 AM, Kees Cook wrote:
>>>
>>> - move page-spanning check behind a CONFIG since it's triggering false
>>> positives
>>
>> Hmm. I pulled this, but looking at
On 09/07/16 12:47, Joe Perches wrote:
> Request for Comment and Work In Progress differences:
>
> Maybe add something like this to Documentation/SubmittingPatches
> ---
> Documentation/SubmittingPatches | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/SubmittingPatch
On Mon, Sep 5, 2016 at 4:31 PM, Bartosz Golaszewski
wrote:
> pca953x_gpio_set_multiple() has some coding style issues that make it
> harder to read. Tweak the code a bit.
>
> Signed-off-by: Bartosz Golaszewski
Much better like this.
Patch applied.
Yours,
Linus Walleij
Changelog:
v6:
move pwms pinctrl to pwms node
fix the order of the dtb file in Makefile
- v5:
- correct the mail format
- v4:
- re-order some nodes in alphabetical order
- fix some minor bugs
- add a entry in vendor list
- v3:
- fixing the rtc clock, using clock source f
The TOPEET itop is a samsung exnynos 4412 core board, which have
two package versions. This patch add the support for SCP version.
Currently supported are USB3503A HSIC, USB OTG, eMMC, rtc and
PMIC. The future features are in the based board. Also MFC and
watchdog have been enabled.
Signed-off-by
Add TOPEET, a ARM devlopment board vendor in China mainland.
Signed-off-by: Randy Li
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt
b/Documentation/devicetree/bindings/vendor-pre
The TOPEET itop exynos 4412 have three versions base board. The
Elite version is the cheap one without too much peripheral devices
on it.
Currently supported are serial console, wired networking(USB),
USB OTG in peripheral mode, USB host, SD storage, GPIO buttons,
PWM beeper, ADC and LEDs. The WM8
On Mon, Sep 5, 2016 at 4:31 PM, Bartosz Golaszewski
wrote:
> There are multiple places in the driver code where a
> switch (chip->chip_type) is used to determine the proper register
> offset.
>
> Unduplicate the code by adding a simple structure holding the possible
> offsets that differ between
On Mon, Sep 5, 2016 at 4:31 PM, Bartosz Golaszewski
wrote:
> I'm working on converting the pca953x driver to using regmap, but since
> it's not a trivial task I figured I'd post a couple refactoring patches
> I did so far for 4.9.
I'm in. I'm also ready to merge more patches on top late, because
On Tue, Sep 6, 2016 at 12:52 AM, Christophe Leroy
wrote:
> of_mm_gpiochip_add_data() calls mm_gc->save_regs() before
> setting the data. Therefore ->save_regs() cannot use
> gpiochip_get_data()
>
> An Oops is encountered without this fix.
>
> fixes: 1e714e54b5ca5 ("powerpc: qe_lib-gpio: use gpioc
On Tue, Sep 6, 2016 at 3:59 PM, Marc Zyngier wrote:
> Using a default trigger is a bad idea if using DT to configure
> interrupts, as the device's interrupt specifier will always contain
> the trigger configuration.
>
> Let's warn about that particular situation, and revert to not
> having a defa
On Tue, Sep 6, 2016 at 10:20 AM, Neil Armstrong wrote:
> To make a slot-in replacement, it misses the sx150x_platform_data management
> like the gpio version, I only made a pure DT version. It should be easy to
> add back.
>
> But I see it nowhere... is it really necessary ?
If that is not used
On Wed, Sep 7, 2016 at 10:12 AM, Marc Zyngier wrote:
> Using a default trigger is a bad idea if using DT to configure
> interrupts, as the device's interrupt specifier will always contain
> the trigger configuration.
>
> Let's warn about that particular situation, and revert to not
> having a def
On Wed, Sep 7, 2016 at 1:31 PM, Sean Paul wrote:
> On Wed, Sep 7, 2016 at 2:13 PM, dbasehore . wrote:
>> On Tue, Sep 6, 2016 at 10:18 AM, Sean Paul wrote:
>>> On Mon, Sep 5, 2016 at 1:06 AM, Lin Huang wrote:
when in ddr frequency scaling process, vop can not do enable or
disable opera
The sdhci controller on xilinx zynq devices will not function unless
the CD bit is provided. http://www.xilinx.com/support/answers/61064.html
In cases where it is impossible to provide the CD bit in hardware,
setting the controller to test mode and then setting inserted to true
will get the control
The sdhci controller on xilinx zynq devices will not function unless
the CD bit is provided. http://www.xilinx.com/support/answers/61064.html
In cases where it is impossible to provide the CD bit in hardware,
setting the controller to test mode and then setting inserted to true
will get the control
On Wed, Sep 07, 2016 at 11:41:44PM +0200, Arnd Bergmann wrote:
> On Thursday, July 21, 2016 1:55:56 PM CEST Hoan Tran wrote:
> > + ctx->comm_base_addr = cppc_ss->base_address;
> > + if (ctx->comm_base_addr) {
> > + ctx->pcc_comm_addr =
> > +
While writing an improved changelog, as prompted by Andrew, for v1 of
"mm: fix cache mode of dax pmd mappings" [1], it struck me that
vmf_insert_pfn_pmd() is implemented correctly. Instead, it is the
memtype tree that is missing a memtype reservation for
devm_memremap_pages() ranges.
vmf_insert_p
track_pfn_insert() in vmf_insert_pfn_pmd() is marking dax mappings as
uncacheable rendering them impractical for application usage. DAX-pte
mappings are cached and the goal of establishing DAX-pmd mappings is to
attain more performance, not dramatically less (3 orders of magnitude).
track_pfn_ins
vm_insert_mixed() unlike vm_insert_pfn_prot() and vmf_insert_pfn_pmd(),
fails to check the pgprot_t it uses for the mapping against the one
recorded in the memtype tracking tree. Add the missing call to
track_pfn_insert() to preclude cases where incompatible aliased mappings
are established for a
On Wed, Sep 07, 2016 at 11:41:44PM +0200, Arnd Bergmann wrote:
> On Thursday, July 21, 2016 1:55:56 PM CEST Hoan Tran wrote:
> > + ctx->comm_base_addr = cppc_ss->base_address;
> > + if (ctx->comm_base_addr) {
> > + ctx->pcc_comm_addr =
> > +
Is there any possibility to get this in to the next Linux release?
Do I need to re-submit?
-corey
On 04/27/2016 08:04 AM, miny...@acm.org wrote:
This is unchanged from v2, just rebased onto a more current kernel.
I haven't heard anything about this. If we could get this functionality
in to th
On Wed, Sep 7, 2016 at 2:24 PM, Jiri Olsa wrote:
>
> I'll give this more testing, but it looks ok so far,
Looks fine to me.
I'd perhaps suggest using a simpler interface than
"__get_free_pages(GFP_KERNEL, 0);".
If nothing else, just drop the "order" argument and use
"__get_free_page()", but may
On 07/09/16 18:03, Dave Gordon wrote:
> On 06/09/16 21:36, Nicolas Iooss wrote:
>> On 06/09/16 12:21, Dave Gordon wrote:
>>> On 04/09/16 19:58, Nicolas Iooss wrote:
When building the kernel with clang and some warning flags, the
compiler
reports that the return value of dcs_get_backl
Adds pm_runtime support for rockchip Type-C, so that power domain is
enabled only when there is a transaction going on to help save power.
Signed-off-by: Chris Zhong
---
Changes in v2:
-- add pm_runtime_put_sync in err case
drivers/phy/phy-rockchip-typec.c | 19 +++
1 file chan
The tcpc power domain will try to power up/down the power of Type-C PHY.
Hence, we need control it in Type-C PHY driver with the pm_runtime helper.
Signed-off-by: Chris Zhong
---
Changes in v2: None
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/
From: Zubair Lutfullah Kakakhel
Date: Mon, 5 Sep 2016 13:07:54 +0100
> The MIPS based xilfpga platform uses this driver.
> Enable it for MIPS
>
> Signed-off-by: Zubair Lutfullah Kakakhel
>
> ---
> V1 -> V6 are from a series that has gotten too big.
> So I have split this patch and am sending i
On Wed, Aug 31, 2016 at 10:25 AM, Milo Kim wrote:
> H3 has single PWM channel. The second PWM channel is not supported,
> so the pinctrl function should be removed.
>
> Cc: Linus Walleij
> Cc: Maxime Ripard
> Cc: Chen-Yu Tsai
> Cc: Icenowy Zheng
> Cc: Jens Kuske
> Cc: Krzysztof Adamski
> Cc
On Wed, Sep 7, 2016 at 11:55 PM, Linus Walleij wrote:
> On Mon, Sep 5, 2016 at 4:31 PM, Bartosz Golaszewski
> wrote:
>
>> pca953x_gpio_set_multiple() has some coding style issues that make it
>> harder to read. Tweak the code a bit.
>>
>> Signed-off-by: Bartosz Golaszewski
>
> Much better like t
On Mon, Sep 5, 2016 at 1:14 PM, wrote:
> From: Robert Foss
>
> Fixed a -> an typo.
>
> Signed-off-by: Robert Foss
Acked-by: Kees Cook
This could be taken directly into the docs tree, I think -- no reason
to make it depend on the rest of the series.
-Kees
> ---
> Documentation/filesystems/
On 09/06/2016 12:05 PM, Steven Rostedt wrote:
> On Tue, 6 Sep 2016 11:49:23 -0600
> Shuah Khan wrote:
>
>> +#if !defined(_TRACE_KOBJECT_H) || defined(TRACE_HEADER_MULTI_READ)
>> +#define _TRACE_KOBJECT_H
>> +
>> +#include
>> +#include
>> +
>> +/* kobject_init_class */
>> +DECLARE_EVENT_CLASS(k
return ret;
> + }
> + }
fw_load_from_user_helper() no longer needs the timeout parameter then.
Given this fact I'll chime in with some other, IMHO cosmetic things for
this series. This however is the just the biggest issue for this series
that I'v
On 09/05/2016 07:24 AM, Paul Burton wrote:
> Commit f70ddc07b637 ("MIPS: c-r4k: Avoid small flush_icache_range SMP
> calls") adds checks to force use of hit-type cache ops for small icache
> flushes where they are globalised & index-type cache ops aren't, in
> order to avoid the overhead of IPIs in
From: Omar Sandoval
Here's v2 of the patch making blk-mq's scalable bitmaps a generic
library, now blown up into 5 patches. v1 is here [1].
Changes since v1:
- Return -EINVAL instead of BUG_ON() if an invalid shift is passed to
the initialization functions.
- Rename last_cache to alloc_hint.
From: Omar Sandoval
Allocating your own per-cpu allocation hint separately makes for an
awkward API. Instead, allocate the per-cpu hint as part of the `struct
scale_bitmap_queue`. There's no point for a `struct scale_bitmap_queue`
without the cache, but you can still use a bare `struct scale_bitm
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