[PATCH v3] PCI: altera: Retrain link in rootport mode only

Altera PCIe IP can be configured as rootport or device and they might have same vendor ID. It will cause the system hang issue if Altera PCIe is in endpoint mode and work with other PCIe rootport that from other vendors. Moved retrain function to before pci_scan_root_bus and removed _FIXUP. Add _al

Re: [RFC PATCH 2/4] perf-probe: Add offline output directory option

On Wed, 24 Aug 2016 09:58:45 -0300 Arnaldo Carvalho de Melo wrote: > Em Wed, Aug 24, 2016 at 02:58:12PM +0900, Masami Hiramatsu escreveu: > > Add offline output direcrtory option. This allows user to > > store probe event definition in offline output directory. > > In such cases you should show

Re: [PATCH] livepatch/module: make TAINT_LIVEPATCH module-specific

Hi Josh, [auto build test ERROR on jikos-livepatching/for-next] [also build test ERROR on v4.8-rc3 next-20160824] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] [Suggest to use git(>=2.9.0) format-patch --base= (or --base=auto for convenie

Re: [PATCH v6 2/4] Add support for SCT Write Same

You only fill the bytes that you want to to set explicitly: + put_unaligned_le16(0x0002, &sctpg[0]); /* SCT_ACT_WRITE_SAME */ + put_unaligned_le16(0x0101, &sctpg[1]); /* WRITE PTRN FG */ + put_unaligned_le64(lba, &sctpg[2]); + put_unaligned_le64(num, &sctpg[6]); +

[PATCH] i2c: mux: mellanox: fix platform_no_drv_owner.cocci warnings

drivers/i2c/muxes/i2c-mux-mlxcpld.c:329:3-8: No need to set .owner here. The core will do it. Remove .owner field if calls are used which set it automatically Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci CC: Vadim Pasternak Signed-off-by: Fengguang Wu --- i2c-mux-mlxcpl

[PATCH 1/2] pwm: sun4i: Add Allwinner H3 support

According to the latest datasheet (v1.2), H3 has single PWM channel. H3 PWM controller has same register layout as sun4i driver, so it works by adding H3 specific data. And the second PWM channel is not supported, so the pinctrl function is removed. Datasheet: http://linux-sunxi.org/File:Allwin

[PATCH 2/2] ARM: dts: sun8i-h3: Add UART1 pinctrl

In H3, PA5 can be used as PWM and UART0. If the PWM is used, the console UART should be moved to other port. This patch enables UART1 pinctrl to support this case. PA5: PWM PG6, PG7: debug console Cc: Chen-Yu Tsai Cc: Maxime Ripard Cc: Rob Herring Signed-off-by: Milo Kim ---

Re: [patch 2/2] i2c: mux: mellanox: add driver

Hi Vadim, [auto build test WARNING on wsa/i2c/for-next] [also build test WARNING on v4.8-rc3 next-20160824] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] [Suggest to use git(>=2.9.0) format-patch --base= (or --base=auto for convenience)

Re: [PATCH v2 2/3] tracing: Add trace_irqsoff tracepoints

Hi Binoy, [auto build test ERROR on tip/perf/core] [also build test ERROR on v4.8-rc3 next-20160824] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] [Suggest to use git(>=2.9.0) format-patch --base= (or --base=auto for convenience) to rec

Re: [PATCH v2 2/3] tracing: Add trace_irqsoff tracepoints

Hi Binoy, [auto build test WARNING on tip/perf/core] [also build test WARNING on v4.8-rc3 next-20160824] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] [Suggest to use git(>=2.9.0) format-patch --base= (or --base=auto for convenience)

[PATCH] net: hns: dereference ppe_cb->ppe_common_cb if it is non-null

From: Colin Ian King ppe_cb->ppe_common_cb is being dereferenced before a null check is being made on it. If ppe_cb->ppe_common_cb is null then we end up with a null pointer dereference when assigning dsaf_dev. Fix this by moving the initialisation of dsaf_dev once we know ppe_cb->ppe_common_cb

[PATCH v2 2/3] clk: samsung: exynos5420: Add clocks for CMU_CDREX domain

This patch adds the mux/divider clocks for CMU_CDREX (DRAM Express Controller) which generates the clocks for DRAM and NoC (Network on Chip) bus clock. But, there is differnet source of MUX_MX_MSPLL_CCORE between exynos5420 and exynos5422. So, each MUX_MX_MSPLL_CCORE uses the different parent sourc

[PATCH v2 1/3] dt-bindings: Add the clock id for CMU_CDREX (DRAM Express Controller)

This patch adds the new clock id for CMU_CDRES (DRAM Express Controller) geneates the clocks for DRAM and NoC (Network on Chip) bus clock. Signed-off-by: Chanwoo Choi --- include/dt-bindings/clock/exynos5420.h | 11 ++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/includ

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