Hi Juri,
On 19/07/16 13:40, Juri Lelli wrote:
Add TC2 cpu capacity binding information.
If you repost it,
s/binding//
Cc: Liviu Dudau
Cc: Sudeep Holla
Acked-by: Sudeep Holla
(assuming you take it via some other tree, let us know if it's
OK to merge the DTS separately and you want us
Commit-ID: b8922125e4790fa237a8a4204562ecf457ef54bb
Gitweb: http://git.kernel.org/tip/b8922125e4790fa237a8a4204562ecf457ef54bb
Author: Xunlei Pang
AuthorDate: Sat, 9 Jul 2016 15:54:22 +0800
Committer: Ingo Molnar
CommitDate: Wed, 10 Aug 2016 13:32:55 +0200
sched/fair: Fix typo in sync_
On 2016-08-09 04:17 PM, Robert Foss wrote:
+static int totmaps_proc_show(struct seq_file *m, void *data)
+{
+struct proc_maps_private *priv = m->private;
+struct mm_struct *mm;
+struct vm_area_struct *vma;
+struct mem_size_stats *mss_sum = priv->mss;
+
+/* reference to priv-
Commit-ID: 31851a9874d63dbb532910a86b2be49c15997ea3
Gitweb: http://git.kernel.org/tip/31851a9874d63dbb532910a86b2be49c15997ea3
Author: Leo Yan
AuthorDate: Fri, 5 Aug 2016 14:31:29 +0800
Committer: Ingo Molnar
CommitDate: Wed, 10 Aug 2016 14:03:32 +0200
sched/fair: Remove 'cpu_busy' par
> One comment: the patch description should be "stand-alone" text, not a
> continuation of the subject. I fixed this.
I see. Will keep that in mind for the future. Thanks!
signature.asc
Description: PGP signature
This adds DT support for the NAND connected to the SoC AEMIF.
The parameters (timings, ecc) are the same as what the board ships with
(default AEMIF timings, 1bit ECC) and improvements will be handled in
due course.
This passed elementary tests hashing a 20MB file on top of ubifs on my
LCDK.
Signe
Hi Stephen,
2016-08-09 8:37 GMT+09:00 Stephen Boyd :
> On 08/08, Masahiro Yamada wrote:
>> Hi Stephen,
>>
>>
>> 2016-08-05 6:25 GMT+09:00 Stephen Boyd :
>> > +Rob in case he has any insight
>> >
>> > On 07/09, Masahiro Yamada wrote:
>> >> Hi.
>> >>
>> >> I think the current code allows to add
>>
Am Mittwoch, 10 August 2016, 13:41:08 schrieb Michael Ellerman:
> Thiago Jung Bauermann writes:
> > Am Dienstag, 09 August 2016, 09:01:13 schrieb Mimi Zohar:
> >> On Tue, 2016-08-09 at 20:59 +1000, Michael Ellerman wrote:
> >> > Mimi Zohar writes:
> >> > > +/* Some details preceding the binary s
On Wednesday 10 August 2016 04:52 AM, Ivan Khoronzhuk wrote:
> The irq data are common for net devs in dual_emac mode. So no need to
> hold these data in every priv struct, move them under cpsw_common.
> Also delete irq_num var, as after optimization it's not needed.
> Correct number of irqs to 2,
On Wednesday 10 August 2016 04:52 AM, Ivan Khoronzhuk wrote:
> The ale, cpts, version, rx_packet_max, bus_freq, interrupt pacing
> parameters are common per net device that uses the same h/w. So,
> move them to common driver structure.
>
> Signed-off-by: Ivan Khoronzhuk
Reviewed-by: Mugunthan V
Commit-ID: c0c8c9fa210c9a042060435f17e40ba4a76d6d6f
Gitweb: http://git.kernel.org/tip/c0c8c9fa210c9a042060435f17e40ba4a76d6d6f
Author: Wanpeng Li
AuthorDate: Thu, 4 Aug 2016 09:42:20 +0800
Committer: Ingo Molnar
CommitDate: Wed, 10 Aug 2016 14:02:55 +0200
sched/deadline: Fix lock pinni
On Tuesday 09 August 2016 05:39 PM, Grygorii Strashko wrote:
> Kmemleak reports following false positive memory leaks for each sk
> buffers allocated by CPSW (__netdev_alloc_skb_ip_align()) in
> cpsw_ndo_open() and cpsw_rx_handler():
>
> unreferenced object 0xea915000 (size 2048):
> comm "system
> > I assume Wolfram will merge this.
>
> I assume not, see http://lwn.net/Articles/696227/
Thanks for the pointer. I missed the discussion but came up with the
same conclusions: a) octals are easier to read and b) original author
should have asked if this change was feasible before posting 1285
On 20/07/16 12:00, Adrian Hunter wrote:
> June 2015 Intel SDM introduced IP Compression types 4 and 6. Refer section
> 36.4.2.2 Target IP (TIP) Packet - IP Compression.
>
> Existing Intel PT packet decoder did not support type 4, and got type 6
> wrong. Because type 3 and type 4 have the same num
While converting the init function to return an error, the wrong clock
was get. This lead to wrong clock rate and slow down the kernel. For
example, before the patch a typical boot was around 15s after it was 1
minute slower.
Fixes: 12549e27c63c ("clocksource/drivers/time-armada-370-xp: Convert in
On 2016-08-09 01:35, Jonathan Corbet wrote:
> Cc: Jan Kiszka
> Signed-off-by: Jonathan Corbet
> ---
> .../gdb-kernel-debugging.rst} | 77
> +-
> Documentation/dev-tools/tools.rst | 1 +
> 2 files changed, 46 insertions(+), 32 deletions(
From: Patrice Chotard
- Remove useless gpio-cells
- Update second parameter by using GPIO_ACTIVE_HIGH/LOW
instead of hardcoded value
Signed-off-by: Patrice Chotard
---
arch/arm/boot/dts/stih41x-b2020.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot
Commit-ID: 9279e0d2e565e0217618c2087de83d3239811329
Gitweb: http://git.kernel.org/tip/9279e0d2e565e0217618c2087de83d3239811329
Author: Luis de Bethencourt
AuthorDate: Sun, 10 Jul 2016 15:00:26 +0100
Committer: Ingo Molnar
CommitDate: Wed, 10 Aug 2016 14:03:32 +0200
sched/core: Add docu
On Wednesday 10 August 2016 04:52 AM, Ivan Khoronzhuk wrote:
> The napi structs are common for both net devices in dual_emac
> mode, In order to not hold duplicate links to them, move to
> cpsw_common.
>
> Signed-off-by: Ivan Khoronzhuk
> ---
Reviewed-by: Mugunthan V N
Regards
Mugunthan V N
2016-08-05 5:57 GMT+09:00 Stephen Boyd :
> On 07/19, Masahiro Yamada wrote:
>> The .get(_hw) callback of an OF clock provider can return a NULL
>> pointer in some cases.
>>
>> For example, of_clk_src_onecell_get() returns NULL for index 1 of a
>> sparse array of clocks like follows:
>>
>> clk_num
Hi Marc, Linus,
On 10/08/16 10:41, Marc Zyngier wrote:
> Hi Linus,
>
> On 10/08/16 00:03, Linus Walleij wrote:
>> On Tue, Aug 9, 2016 at 3:20 PM, Jon Hunter wrote:
>>
>>> If that works, then does the following also work (without the above) ...
>>>
>>> diff --git a/kernel/irq/chip.c b/kernel/irq/
From: Matt Roper
When we write watermark values to the hardware, those values are stored
in dev_priv->wm.skl_hw. However with recent watermark changes, the
results structure we're copying from only contains valid watermark and
DDB values for the pipes that are actually changing; the values for
o
Em Wed, Aug 10, 2016 at 07:28:08AM +0900, Masami Hiramatsu escreveu:
> Hi Ingo,
>
> Could you add my Acked-by for this patch?
> (I thought I've sent it...)
Sorry about that, I usually put those acks diligently, but this one
slipped by... I saw the discussion, waited for it to settle and you ack
t
On Wed, Aug 10, 2016 at 10:45:51AM -0700, Sonny Rao wrote:
> On Wed, Aug 10, 2016 at 10:37 AM, Jann Horn wrote:
> > On Wed, Aug 10, 2016 at 10:23:53AM -0700, Sonny Rao wrote:
> >> On Tue, Aug 9, 2016 at 2:01 PM, Robert Foss
> >> wrote:
> >> >
> >> >
> >> > On 2016-08-09 03:24 PM, Jann Horn wrote
Commit-ID: 2db34e8bf9a22f4e38b29deccee57457bc0e7d74
Gitweb: http://git.kernel.org/tip/2db34e8bf9a22f4e38b29deccee57457bc0e7d74
Author: pan xinhui
AuthorDate: Mon, 18 Jul 2016 17:47:39 +0800
Committer: Ingo Molnar
CommitDate: Wed, 10 Aug 2016 14:13:27 +0200
locking/qrwlock: Fix write un
Hi Borislav
On 4 August 2016 at 17:48, Borislav Petkov wrote:
> On Fri, Jul 29, 2016 at 04:57:44PM +0800, fu@linaro.org wrote:
>> From: Tomasz Nowicki
>>
>> This commit provides APEI arch-specific bits for aarch64
>>
>> Meanwhile,
>> (1)add a new subfunction "hest_ia32_init" for
>> "acpi_dis
Commit-ID: eaecf41f5abf80b63c8e025fcb9ee4aa203c3038
Gitweb: http://git.kernel.org/tip/eaecf41f5abf80b63c8e025fcb9ee4aa203c3038
Author: Morten Rasmussen
AuthorDate: Wed, 22 Jun 2016 18:03:14 +0100
Committer: Ingo Molnar
CommitDate: Wed, 10 Aug 2016 14:03:32 +0200
sched/fair: Optimize fi
If we're enabling a pipe, we'll need to modify the watermarks on all
active planes. Since those planes won't be added to the state on
their own, we need to add them ourselves.
Signed-off-by: Lyude
Reviewed-by: Matt Roper
Cc: sta...@vger.kernel.org
Cc: Ville Syrjälä
Cc: Daniel Vetter
Cc: Radhak
Fix exynos_drm_gem_create() error messages to include flags and size when
flags and size are invalid.
Signed-off-by: Shuah Khan
---
drivers/gpu/drm/exynos/exynos_drm_gem.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_gem.c
b/drivers/g
On Wed, 2016-08-10 at 10:43 +0100, Russell King - ARM Linux wrote:
> On Fri, Jun 03, 2016 at 11:40:24AM -0700, Kees Cook wrote:
> >
> > @@ -1309,16 +1309,11 @@ void __init arm_mm_memblock_reserve(void)
> > * Any other function or debugging method which may touch any
> > device _will_
> > * cra
On Wed, Aug 10, 2016 at 02:01:57PM +0530, Sekhar Nori wrote:
> On Tuesday 09 August 2016 10:45 PM, Karl Beldan wrote:
> > This adds DT support for the NAND connected to the SoC AEMIF.
> > The parameters (timings, ecc) are the same as what the board ships with
> > (default AEMIF timings, 1bit ECC) a
On 08/10/2016 05:29 AM, Peter Zijlstra wrote:
On Tue, Aug 09, 2016 at 02:00:00PM -0400, Waiman Long wrote:
Alternative might be to use the LSB of mutex::owner, but that's going to
be somewhat icky too.
I was thinking about doing that. However, the owner field is used in quite a
number of places
Commit-ID: 08be8f63c40c030b5cf95b4368e314e563a86301
Gitweb: http://git.kernel.org/tip/08be8f63c40c030b5cf95b4368e314e563a86301
Author: Waiman Long
AuthorDate: Tue, 31 May 2016 12:53:47 -0400
Committer: Ingo Molnar
CommitDate: Wed, 10 Aug 2016 14:16:02 +0200
locking/pvstat: Separate wai
Hi,
On 08/10/2016 10:14 AM, Tejun Heo wrote:
Hello, Tom.
On Wed, Aug 10, 2016 at 06:04:10PM +0800, Tom Yan wrote:
On 10 August 2016 at 11:26, Tejun Heo wrote:
Hmmm.. why not? The hardware limit is 64k and the driver is using a
Is that referring to the maximum number of entries allowed in
Thanks to Ville for suggesting this as a potential solution to pipe
underruns on Skylake.
On Skylake all of the registers for configuring planes, including the
registers for configuring their watermarks, are double buffered. New
values written to them won't take effect until said registers are
"ar
Hi Florian,
Thanks for the review...
> >
> > This converter sits between the MAC and the external phy MAC <==>
> > GMII2RGMII <==> RGMII_PHY
>
> This looks good, just a few things, see below:
Thanks...
> > +config XILINX_GMII2RGMII
> > + tristate "Xilinx GMII2RGMII converter driv
On Tue, Aug 09, 2016 at 01:36:17PM +0200, Wolfram Sang wrote:
> The core will do this for us now.
>
> Signed-off-by: Wolfram Sang
> ---
[...]
> drivers/i2c/busses/i2c-at91.c | 2 --
Acked-by: Ludovic Desroches
[...]
> diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses
From: Rafał Miłecki
This clock is present on cheaper Northstar devices like BCM53573 or
BCM47189 using Corex-A7. ILP is a part of PMU (Power Management Unit)
and so it should be defined as one of its subnodes (subdevices). For
more details see Documentation entry.
Unfortunately there isn't a set
ping?
On Thu, Jul 14, 2016 at 10:18 PM, Ricardo Ribalda Delgado
wrote:
> Xilinx Spartan-3AN FPGAs contain an In-System Flash where they keep
> their configuration data and (optionally) some user data.
>
> The protocol of this flash follows most of the spi-nor standard. With
> the following differ
Changes from v1:
- s/cs2/cs3
- kept "ti,.." only nand properties (the adjustments made by
nand_davinci_probe are broken)
- replaced v1_1/4:
"memory: ti-aemif: Get a named clock rather than an unnamed one"
with v2_1/4:
"davinci: da8xx-dt: Add ti-aemif lookup for clock matching"
-
Parse devicetree parameters for voltage and prescaler setting. This allows
using multiple max6550 devices with varying settings, and also makes it
possible to instantiate and configure the device using devicetree.
Signed-off-by: Mike Looijmans
---
v3: Resubmit because mailing lists bounced
Fi
Commit-ID: 469f00231278da68062a809306df0bac95a27507
Gitweb: http://git.kernel.org/tip/469f00231278da68062a809306df0bac95a27507
Author: Alexander Potapenko
AuthorDate: Fri, 15 Jul 2016 11:42:43 +0200
Committer: Ingo Molnar
CommitDate: Wed, 10 Aug 2016 14:19:33 +0200
x86, kasan, ftrace:
On 三, 2016-08-10 at 02:54 +, Kuninori Morimoto wrote:
> Hi Zhang
>
> >
> > >
> > > Hi Linux-PM, Linux-Kernel ML
> > >
> > > I posted thermal driver patch 2month ago, but no response and
> > > nothing
> > > happen.
> > > I'm following scripts/get_maintainer.pl, but am I wrong ??
> > > Who is
On Wed, 10 Aug 2016, Sylwester Nawrocki wrote:
> On 08/09/2016 10:50 PM, Lee Jones wrote:
> > On Tue, 09 Aug 2016, Sylwester Nawrocki wrote:
> >
> >> > On 08/09/2016 05:05 PM, Lee Jones wrote:
> > >> +static SIMPLE_DEV_PM_OPS(lpass_pm_ops, exynos_lpass_suspend,
> > > >> > +
On Wed, Aug 10, 2016 at 5:56 AM, Tom Yan wrote:
> On 10 August 2016 at 09:00, Shaun Tancheff wrote:
>> static unsigned int ata_scsi_write_same_xlat(struct ata_queued_cmd *qc)
>> {
>> struct ata_taskfile *tf = &qc->tf;
>> struct scsi_cmnd *scmd = qc->scsicmd;
>> struct at
On Wed, 10 Aug 2016 07:39:08 +0800
Wanpeng Li wrote:
> The regression is caused by your commit "sched,time: Count actually
> elapsed irq & softirq time".
Wanpeng, does this patch fix your issue?
Paolo, what is your opinion on this issue?
I can think of all kinds of ways in which guest and host
Hi Thomas,
On 09/08/2016 11:19, Thomas Gleixner wrote:
> On Tue, 2 Aug 2016, Eric Auger wrote:
>
>> Currently the MSI message is composed by directly calling
>> irq_chip_compose_msi_msg and erased by setting the memory to zero.
>>
>> On some platforms, we will need to complexify this composition
Now that we can hook into update_crtcs and control the order in which we
update CRTCs at each modeset, we can finish the final step of fixing
Skylake's watermark handling by performing DDB updates at the same time
as plane updates and watermark updates.
The first major change in this patch is skl_
Hello Shuah,
On 08/08/2016 07:48 PM, Shuah Khan wrote:
> Fix unsupported GEM memory type error message to include the memory type
> information.
>
> Signed-off-by: Shuah Khan
> ---
> Changes since v1:
> -- Comment changed to read clearly
>
> drivers/gpu/drm/exynos/exynos_drm_fb.c | 6 +++---
>
Thiago Jung Bauermann writes:
> Am Mittwoch, 10 August 2016, 13:41:08 schrieb Michael Ellerman:
>> Thiago Jung Bauermann writes:
>> > Am Dienstag, 09 August 2016, 09:01:13 schrieb Mimi Zohar:
>> >> On Tue, 2016-08-09 at 20:59 +1000, Michael Ellerman wrote:
>> >> > Mimi Zohar writes:
>> >> > >
Commit-ID: c7d2361f7524f365c1ae42f47880e3fa9efb2c2a
Gitweb: http://git.kernel.org/tip/c7d2361f7524f365c1ae42f47880e3fa9efb2c2a
Author: Thomas Garnier
AuthorDate: Tue, 9 Aug 2016 10:11:04 -0700
Committer: Ingo Molnar
CommitDate: Wed, 10 Aug 2016 14:45:19 +0200
x86/mm/KASLR: Fix physical
On Wednesday 10 August 2016 04:52 AM, Ivan Khoronzhuk wrote:
> The pointers on h/w registers are common for every cpsw_private
> instance, so no need to hold them for every ndev.
>
> Signed-off-by: Ivan Khoronzhuk
Reviewed-by: Mugunthan V N
Regards
Mugunthan V N
Thanks to Ville for suggesting this as a potential solution to pipe
underruns on Skylake.
On Skylake all of the registers for configuring planes, including the
registers for configuring their watermarks, are double buffered. New
values written to them won't take effect until said registers are
"ar
Commit-ID: 22ac2bca92f2d92c6495248d65ff648182df428d
Gitweb: http://git.kernel.org/tip/22ac2bca92f2d92c6495248d65ff648182df428d
Author: Mike Travis
AuthorDate: Mon, 1 Aug 2016 13:40:52 -0500
Committer: Ingo Molnar
CommitDate: Wed, 10 Aug 2016 15:55:38 +0200
x86/platform/UV: Fix problem
Changes since v3
* The first part with cleanups (v4, v5) went separately to 4.8-rc1
* Rebased to 4.8-rc1
* Patch 1 - don't touch cached pfns in whole-zone compaction (Joonsoo)
* New patches 2 and 3 in response to Joonsoo pointing out missing adustments
to watermark checks in patch 7 - turns out w
From: Sunil Goutham
This patch adds support for BGX module on 81xx where a BGX
can be split and have different LMACs configured in
different modes.
Signed-off-by: Sunil Goutham
---
drivers/net/ethernet/cavium/thunder/thunder_bgx.c | 112 --
drivers/net/ethernet/cavium/thund
dmatest on ARC SDP with DW DMAC became broken after df5c7386
("dmaengine: dw: some Intel devices has no memcpy support") and
30cb2639 ("dmaengine: dw: don't override platform data with autocfg")
commits.
* After df5c7386 commit "DMA_MEMCPY" capability option doesn't
get set correctly in platform dr
* Baoquan He wrote:
> ACPI MADT has a 32-bit field providing lapic address at which
> each processor can access its lapic information. MADT also contains
> an optional entry to provide a 64-bit address to override the 32-bit
> one. However the current code does the lapic address override entry
>
Em Wed, Aug 10, 2016 at 03:36:16PM +0200, Rabin Vincent escreveu:
> From: Rabin Vincent
>
> When using split debug info, the file without debug info may not have a
> .debug_frame section, so we need to check the symsrc ELF also, since
> that's the file we actually read the unwind information from
Commit-ID: 25dfe4785332723f09311dcb7fd91015a60c022f
Gitweb: http://git.kernel.org/tip/25dfe4785332723f09311dcb7fd91015a60c022f
Author: Thomas Garnier
AuthorDate: Wed, 27 Jul 2016 08:59:56 -0700
Committer: Ingo Molnar
CommitDate: Wed, 10 Aug 2016 16:10:06 +0200
x86/mm/64: Enable KASLR f
On Wed, Aug 10, 2016 at 10:23:53AM -0700, Sonny Rao wrote:
> On Tue, Aug 9, 2016 at 2:01 PM, Robert Foss wrote:
> >
> >
> > On 2016-08-09 03:24 PM, Jann Horn wrote:
> >>
> >> On Tue, Aug 09, 2016 at 12:05:43PM -0400, robert.f...@collabora.com wrote:
> >>>
> >>> From: Sonny Rao
> >>>
> >>> This is
On 08 August 2016 12:06, Steve Twiss wrote:
> On 05 August 2016 10:05, Lee Jones wrote:
> > On Wed, 06 Jul 2016, Steve Twiss wrote:
> > > From: Steve Twiss
> > >
> > > Clearance of any the persistent information within the DA9053 FAULT_LOG
> > > register must be completed during start-up so the
On Fri, Aug 05, 2016 at 06:59:35PM -0500, Alex Thorlton wrote:
> This is a simple change to add in the physical mappings as well as the
> virtual mappings in efi_map_region_fixed. The motivation here is to
> get access to EFI runtime code that is only available via the 1:1
> mappings on a kexec'd
Signed-off-by: John Garry
---
drivers/scsi/hisi_sas/hisi_sas.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h
index 4ae864d..fc51e87 100644
--- a/drivers/scsi/hisi_sas/hisi_sas.h
+++ b/drivers/scsi/hisi_sas/h
On Wed, Aug 10, 2016 at 02:43:50PM +0800, Baolin Wang wrote:
> Hi Peter,
>
> On 10 August 2016 at 14:18, Peter Chen wrote:
> > On Wed, Aug 10, 2016 at 10:33:31AM +0800, Baolin Wang wrote:
> >> Hi Greg,
> >>
> >> On 9 August 2016 at 18:26, Greg KH wrote:
> >> > On Tue, Aug 09, 2016 at 05:33:33PM
When the port is detached we cannot execute a TMF,
as there can be no device attached to the port.
Signed-off-by: John Garry
---
drivers/scsi/hisi_sas/hisi_sas_main.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c
b/drivers/scsi/hisi_sa
Commit-ID: 22cc1ca3c5469cf17e149be232817b9223afa5e4
Gitweb: http://git.kernel.org/tip/22cc1ca3c5469cf17e149be232817b9223afa5e4
Author: Arnd Bergmann
AuthorDate: Tue, 9 Aug 2016 21:54:53 +0200
Committer: Ingo Molnar
CommitDate: Wed, 10 Aug 2016 14:37:06 +0200
x86/hpet: Fix /dev/rtc brea
On Tue, Aug 09, 2016 at 01:27:03AM -0400, Tejun Heo wrote:
> From 471f89b317a21a78dacaee85957984b9f11e79e4 Mon Sep 17 00:00:00 2001
> From: Tejun Heo
> Date: Tue, 9 Aug 2016 01:11:13 -0400
>
> Debugging what goes wrong with cgroup setup can get hairy. Add
> tracepoints for cgroup hierarchy mount
From: Joonsoo Kim
There is a memory waste problem if we define field on struct page_ext
by hard-coding. Entry size of struct page_ext includes the size of
those fields even if it is disabled at runtime. Now, extra memory request
at runtime is possible so page_owner don't need to define it's own f
If get_maintainer is not given any filename arguments on the command line,
the standard input is read for a patch.
But checking if a VCS has a file named &STDIN is not a good idea and fails.
Verify the nominal input file is not &STDIN before checking the VCS.
Fixes: 4cad35a7ca69 ("get_maintainer
Use of_property_read_bool instead of open-coding it as fpcu_has. Convert
the members of struct cpuinfo from u32 to bool accordingly as they are
only used as boolean anyhow.
Signed-off-by: Tobias Klauser
---
arch/nios2/include/asm/cpuinfo.h | 8
arch/nios2/kernel/cpuinfo.c | 15 +++
Commit-ID: fb754f958f8e46202c1efd7f66d5b3db1208117d
Gitweb: http://git.kernel.org/tip/fb754f958f8e46202c1efd7f66d5b3db1208117d
Author: Thomas Garnier
AuthorDate: Tue, 9 Aug 2016 10:11:05 -0700
Committer: Ingo Molnar
CommitDate: Wed, 10 Aug 2016 14:45:19 +0200
x86/mm/KASLR: Increase BRK
Commit-ID: 5a52e8f822374bebc702bb2688ed8b5515bbb55b
Gitweb: http://git.kernel.org/tip/5a52e8f822374bebc702bb2688ed8b5515bbb55b
Author: Mike Travis
AuthorDate: Mon, 1 Aug 2016 13:40:53 -0500
Committer: Ingo Molnar
CommitDate: Wed, 10 Aug 2016 15:55:39 +0200
x86/platform/UV: Fix kernel p
This patchset introduces support for the internal abort
feature for the HiSilicon SAS controller.
The internal abort feature allows commands which are active
in the controller to be aborted before being sent to the
slave device.
Only support will be added for v2 HW since v1 HW has issues
in suppo
When fadump is enabled, by default 5% of system RAM is reserved for
fadump kernel. While that works for most cases, it is not good enough
for every case.
Currently, to override the default value, fadump supports specifying
memory to reserve with fadump_reserve_mem=size, where only a fixed size
can
The dev *ss is stored both in sun4i_tfm_ctx and sun4i_req_ctx.
Since this pointer will never be changed during tfm life, it is better
to remove it from sun4i_req_ctx.
Signed-off-by: LABBE Corentin
---
drivers/crypto/sunxi-ss/sun4i-ss-hash.c | 13 +++--
drivers/crypto/sunxi-ss/sun4i-ss.h
On Tue 09 Aug 11:10 PDT 2016, Lee Jones wrote:
> On Tue, 09 Aug 2016, Bjorn Andersson wrote:
>
> > On Thu 04 Aug 02:21 PDT 2016, Lee Jones wrote:
> >
> > > These types of error prints are superfluous. The system will
> > > pick up on OOM issues and let the user know.
> > >
> > > Signed-off-by:
Since we have to write ddb allocations at the same time as we do other
plane updates, we're going to need to be able to control the order in
which we execute modesets on each pipe. The easiest way to do this is to
just factor this section of intel_atomic_commit_tail()
(intel_atomic_commit() for sta
Commit-ID: aa877175e7a9982233ed8f10cb4bfddd78d82741
Gitweb: http://git.kernel.org/tip/aa877175e7a9982233ed8f10cb4bfddd78d82741
Author: Boris Ostrovsky
AuthorDate: Wed, 3 Aug 2016 13:22:28 -0400
Committer: Ingo Molnar
CommitDate: Wed, 10 Aug 2016 15:42:57 +0200
cpu/hotplug: Prevent allo
On Wed, Aug 10, 2016 at 4:22 PM, Alexander Potapenko wrote:
> Commit the script that symbolizes BUG messages and KASAN error reports
> by adding file:line information to each stack frame.
> The script is a copy of
> https://github.com/google/sanitizers/blob/master/address-sanitizer/tools/kasan_sym
On Mon, Aug 08, 2016 at 05:35:00PM -0600, Jonathan Corbet wrote:
> Cc: Catalin Marinas
> Signed-off-by: Jonathan Corbet
> ---
> .../{kmemleak.txt => dev-tools/kmemleak.rst} | 93
> --
> Documentation/dev-tools/tools.rst | 1 +
> MAINTAINERS
From: Patrice Chotard
- Remove useless gpio-cells
- Update second parameter by using GPIO_ACTIVE_HIGH/LOW
instead of hardcoded value
Signed-off-by: Patrice Chotard
---
arch/arm/boot/dts/stih418-b2199.dts | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot
On Tue, Aug 09, 2016 at 05:15:15PM +, Karl Beldan wrote:
> Many davinci boards (da830 and da850 families) don't have their clocks
> in DT yet and won't be successful in getting an unnamed aemif clock.
> Also the sole current users of ti-aemif (keystone boards) use 'aemif' as
> their aemif devic
On 10 August 2016 at 17:07, Peter Chen wrote:
> On Wed, Aug 10, 2016 at 02:43:50PM +0800, Baolin Wang wrote:
>> Hi Peter,
>>
>> On 10 August 2016 at 14:18, Peter Chen wrote:
>> > On Wed, Aug 10, 2016 at 10:33:31AM +0800, Baolin Wang wrote:
>> >> Hi Greg,
>> >>
>> >> On 9 August 2016 at 18:26, Gre
Commit-ID: e363d24c2b997c421476c6aa00547edadf678efe
Gitweb: http://git.kernel.org/tip/e363d24c2b997c421476c6aa00547edadf678efe
Author: Mike Travis
AuthorDate: Mon, 1 Aug 2016 13:40:51 -0500
Committer: Ingo Molnar
CommitDate: Wed, 10 Aug 2016 15:55:38 +0200
x86/platform/UV: Fix bug with
On Wed, Aug 10, 2016 at 8:05 AM, Rafał Miłecki wrote:
> From: Rafał Miłecki
>
> This clock is present on cheaper Northstar devices like BCM53573 or
> BCM47189 using Corex-A7. ILP is a part of PMU (Power Management Unit)
> and so it should be defined as one of its subnodes (subdevices). For
> more
cpu_ops is initialized once by cpu_read_ops(), and thereafter is mostly
read in hot path, such as arm_cpuidle_suspend().
The fact that it is mostly read and not written to makes it candidates
for __read_mostly declarations.
Signed-off-by: Jisheng Zhang
---
arch/arm64/kernel/cpu_ops.c | 2 +-
1
Currently the davinci da8xx boards use the mach-davinci aemif code.
Instantiating an aemif node into the DT allows to use the ti-aemif
memory driver and is another step to better DT support.
This change adds an aemif node in the dtsi while retiring the nand_cs3
node. The NAND is now instantiated in
This series was initially sent to add support for two PCIe
ports in dra7. This included selecting PCI_DOMAINS config
in SOC_DRA7XX.
However from the review, PCI_DOMAINS can instead be selected
from ARCH_MULTIPLATFORM. This is fixed in this series along
with removing PCI_DOMAINS from other configs.
On Fri, Jun 03, 2016 at 11:40:24AM -0700, Kees Cook wrote:
> @@ -1309,16 +1309,11 @@ void __init arm_mm_memblock_reserve(void)
> * Any other function or debugging method which may touch any device _will_
> * crash the kernel.
> */
> +static char vectors[PAGE_SIZE * 2] __ro_after_init __aligne
This patch adds the support to the new iATU mechanism that will be used
from Core version 4.80, which is called iATU Unroll.
The new Cores can support the iATU Unroll or support the "old" iATU
method now called Legacy Mode. The driver is perfectly capable of
performing well for both.
In order to
On 08/10/2016 02:06 PM, Linus Torvalds wrote:
On Tue, Aug 9, 2016 at 10:39 PM, kernel test robot
wrote:
[ 1537.558739] nfsd: last server has exited, flushing export cache
[ 1540.627795] BUG: Dentry 880027d7c540{i=1846f,n=0a} still in use (1)
[unmount of btrfs vda]
[ 1540.633915]
It is likely that checking the result of 'pm_runtime_set_active' is
expected here.
Fixes: f0e5f57d3ac2 ("iio: light: us8152d: Add power management support")
Signed-off-by: Christophe JAILLET
---
drivers/iio/light/us5182d.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/driv
patch1 is a trivial clean up: move the parameters for wait for link
into the core pcie-designware.c
Since link may be UP but still in link training, if so, we can't think
the link is up and operating correctly. So patch2 teaches
dw_pcie_link_up() beware of the PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING bi
On 10.08.2016 03:10, Luis R. Rodriguez wrote:
> On Thu, Aug 04, 2016 at 02:27:16PM +0200, Daniel Wagner wrote:
>> From: Daniel Wagner
>> In [0] we have a discussion on how the firmware_class API might be
>> changed to improve the current handling of firmware loading. This
>> patch was part of the
yes, you right. If we remove this message there is no big problem. But
if we do not remove this it's also ok, right ? What the big deal to
remove this type of messages (i'm just interested) ?
For me it's ok to remove:
Acked-by: Abylay Ospan
2016-08-09 10:58 GMT-04:00 Wolfram Sang :
>
>> Someti
On Tue, 2016-08-02 at 20:15 +0200, Heinrich Schuchardt wrote:
> i is defined as int but output as %u several times.
> Adjust the format identifiers.
>
> v2:
> Keep definition of i as int.
> David indicated that this is the preferable way to define
> loop variables.
>
> Sig
patch1 is a trivial clean up: move the parameters for wait for link
into the core pcie-designware.c
Since link may be UP but still in link training, if so, we can't think
the link is up and operating correctly. So patch2 teaches
dw_pcie_link_up() beware of the PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING bi
cpuidle_ops is initialized once by arm_cpuidle_read_ops() during
initialization, and thereafter is mostly read in arm_cpuidle_suspend()
The fact that it is mostly read and not written to makes it candidates
for __read_mostly declarations.
Signed-off-by: Jisheng Zhang
---
arch/arm/kernel/cpuidle
On Wed, Aug 10, 2016 at 1:44 PM, Ray Jui wrote:
>
>
> On 8/10/2016 10:28 AM, Rafał Miłecki wrote:
>>
>> On 10 August 2016 at 19:22, Jon Mason wrote:
>>>
>>> On Wed, Aug 10, 2016 at 8:05 AM, Rafał Miłecki wrote:
diff --git a/Documentation/devicetree/bindings/clock/brcm,ns-ilp.txt
b
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