On 11/07/16 10:33, Juergen Gross wrote:
> On 11/07/16 04:51, Bin Wu wrote:
>> During scsi command queueing, if mapping data fails, we need to
>> reclaim the failed request. Otherwise, the garbage request will
>> be pushed into the ring for the backend to work.
>
> Well spotted. There is another in
Hi Konstantin, Xunlei,
2016-07-11 16:42 GMT+08:00 Xunlei Pang :
> On 2016/07/11 at 16:22, Xunlei Pang wrote:
>> On 2016/07/11 at 15:25, Wanpeng Li wrote:
>>> 2016-06-16 20:57 GMT+08:00 Konstantin Khlebnikov
>>> :
Hierarchy could be already throttled at this point. Throttled next
buddy co
On Wed, Jun 22, 2016 at 06:03:15PM +0100, Morten Rasmussen wrote:
> Add a topology flag to the sched_domain hierarchy indicating
> sched_groups at this sched_domain level having different per cpu
> capacity (e.g. big.LITTLE big-only and little-only groups) or groups in
> sibling domains with differ
On 11/07/16 11:50, David Vrabel wrote:
> On 11/07/16 10:33, Juergen Gross wrote:
>> On 11/07/16 04:51, Bin Wu wrote:
>>> During scsi command queueing, if mapping data fails, we need to
>>> reclaim the failed request. Otherwise, the garbage request will
>>> be pushed into the ring for the backend to
On Tue, May 03, 2016 at 10:56:49AM -0500, Franklin S Cooper Jr wrote:
> Now that the node name has been changed from ehrpwm to pwm the document
> should show this proper usage. Change the unit address in the example
> from 0 to the proper physical address value that should be used. Also
> insure th
On Tue, May 03, 2016 at 10:56:50AM -0500, Franklin S Cooper Jr wrote:
> Replace unit address from 0 to the proper physical address. Also insure
> that the unit address matches the reg property address.
>
> Signed-off-by: Franklin S Cooper Jr
> ---
> Documentation/devicetree/bindings/pwm/pwm-tiec
From: Sunil Goutham
This patch series adds support for VNIC on 81xx and 83xx SOCs.
81xx/83xx is different from 88xx in terms of capabilities and different
types of interfaces supported (eg: QSGMII, RGMII) and have DLMs instead
of QLMs which allows single BGX to have interfaces of different LMAC
From: Sunil Goutham
This patch adds PCI device IDs of VNIC on newer chips and also
registers VF driver with them. Device id remains same for all
versions of chips but subsystem device id changes.
Signed-off-by: Sunil Goutham
---
drivers/net/ethernet/cavium/thunder/nic.h| 10 +-
From: Sunil Goutham
This patch adds RGX/RGMII interface type support to BGX
driver. This type of interface is supported by 81xx SOC.
CN81XX VNIC has 8 VFs and max possible LMAC interfaces are 9,
hence RGMII interface will not work if all DLMs are in BGX mode
and all 8 LMACs are enabled.
Signed-
From: Sunil Goutham
This patch adds support for BGX module on 81xx where a BGX
can be split and have different LMACs configured in
different modes.
Signed-off-by: Sunil Goutham
---
drivers/net/ethernet/cavium/thunder/thunder_bgx.c | 112 --
drivers/net/ethernet/cavium/thund
From: Jerin Jacob
When SQ/TXQ is reclaimed i.e reset it's stats also automatically reset
by HW. This is not the case with RQ. Also VF doesn't have write access
to statistics counter registers. Hence a new Mbox msg is introduced which
supports resetting RQ, SQ and full Qset stats. Currently only R
From: Sunil Goutham
Instead of a round about way of converting buffers to SKBs and
combining them into a frag list, use standard skb_add_rx_frag()
API to merge page fragments. This code is useful when incoming
packets are of size more than RCV_FRAG_LEN which is currently
set to 2048bytes.
Signed
From: Sunil Goutham
On 88xx all LMACs in a BGX will be in same mode but on 81xx
BGX can be split as two and there can be LMACs configured in
different modes.
These changes move lmac_type, lane2serdes fields into per lmac
struct from BGX struct. Got rid of qlm_mode field which has become
redundan
On 2016/7/8 10:58, oulijun wrote:
在 2016/7/2 17:39, Lijun Ou 写道:
The HiSilicon Network Substem is a long term evolution IP which is
supposed to be used in HiSilicon ICT SoCs. HNS (HiSilicon Network
Sybsystem) also has a hardware support of performing RDMA with
RoCEE.
The driver for HiSilicon R
From: Radoslaw Biernacki
Adding debug messages in case of NACK for a mailbox message, also
did small cleanups.
Signed-off-by: Radoslaw Biernacki
Signed-off-by: Sunil Goutham
---
drivers/net/ethernet/cavium/thunder/nic_main.c | 16 ++--
drivers/net/ethernet/cavium/thunder/nicvf_m
From: Sunil Goutham
Set MAC addresses only for primary VF's and don't for
secondary VFs.
Signed-off-by: Sunil Goutham
---
drivers/net/ethernet/cavium/thunder/nic_main.c | 2 +-
drivers/net/ethernet/cavium/thunder/nicvf_main.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --g
On Thu, Jul 07, 2016 at 09:58:16PM +0900, Masanari Iida wrote:
> This patch fix double words "the the" in crypto-API.tmpl.
>
> Signed-off-by: Masanari Iida
Patch applied. Thanks.
--
Email: Herbert Xu
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/
From: Sunil Goutham
This patch adds info on HW maximums of 81xx/83xx and also
configures receive and transmit datapaths accordingly.
Signed-off-by: Sunil Goutham
---
drivers/net/ethernet/cavium/thunder/nic_main.c| 87 ++-
drivers/net/ethernet/cavium/thunder/nic_reg.h
Hi Jorge,
On 08/07/2016 09:11, Jorge Ramirez-Ortiz wrote:
> Enable support for higher baud rates (up to 3Mbps) in UART1 - required
> for bluetooth transfers.
>
> Signed-off-by: Jorge Ramirez-Ortiz
> Tested-by: Jorge Ramirez-Ortiz
Fine to me.
Thanks!
Acked-by: Wei Xu
Best Regards,
Wei
> ---
From: Sunil Goutham
81xx has only 4 CPUs, so it doesn't make sense to initialize
entire Qset i.e 8 queues by default. Made changes to queue
initialization to init queues equal to number of CPUs or
8 queues whichever is lesser. Also this will be applicable to
VMs with VNIC VF attached and having l
From: Sunil Goutham
Unlike 88xx, CQE_RX descriptor's tunnelling extension i.e CQE_RX2_S
is always enabled on 81xx/83xx and HW does insert these fields into
CQE_RX. As a result receive buffer addresses will now be present at
7th word of CQE_RX instead of 6th.
Enable CQE_RX2_S on 88xx pass 2.x as
>
>> Sorry, why you still say this 'init_device_table_dma' can block DMA?
>> I just think this function will enable DMA transfer, since we set
>> the V and TV bits, right? or I misunderstand what "block DMA" mean?
>
> When the V and TV bits are not set, it means that all DMA from that
> device-id
On Mon, Jul 11, 2016 at 11:56:23AM +0200, Thierry Reding wrote:
> On Tue, May 03, 2016 at 10:56:50AM -0500, Franklin S Cooper Jr wrote:
> > Replace unit address from 0 to the proper physical address. Also insure
> > that the unit address matches the reg property address.
> >
> > Signed-off-by: Fra
From: Sunil Goutham
Current driver has most of the HW maximums info like no of channels,
traffic limiters, RSS indices e.t.c in the form of macros. These have
been moved into a 'hw_info' structure so that support for VNIC on
newer chips with different set of HW maximums can be added.
Signed-off-
Hi,
On Sun, Jun 26, 2016 at 02:55:48PM -0700, Andy Lutomirski wrote:
> If an arch opts in by setting CONFIG_THREAD_INFO_IN_TASK_STRUCT,
> then thread_info is defined as a single 'u32 flags' and is the first
> entry of task_struct. thread_info::task is removed (it serves no
> purpose if thread_inf
Hi,
[auto build test WARNING on kbuild/for-next]
[also build test WARNING on v4.7-rc7 next-20160708]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Alexey-Dobriyan/CFLAGS-add-Wunused-but-set-par
On 07/10/2016 03:47 PM, Andy Lutomirski wrote:
> Hi all-
>
> I found two nasty issues with virtually mapped stacks if KASAN is
> enabled. The first issue is a crash: the first non-init stack is
> allocated and accessed before KASAN initializes its zero shadow
> AFAICT, which means that we switc
On Wed, Jun 22, 2016 at 06:03:16PM +0100, Morten Rasmussen wrote:
> Systems with the SD_ASYM_CPUCAPACITY flag set indicate that sched_groups
> at this level or below do not include cpus of all capacities available
> (e.g. group containing little-only or big-only cpus in big.LITTLE
> systems). It is
From: Sunil Goutham
This patch adds support for QSGMII interface type to
the BGX driver. This type of interface is supported by
81xx SOC.
Signed-off-by: Sunil Goutham
---
drivers/net/ethernet/cavium/thunder/thunder_bgx.c | 55 ++-
drivers/net/ethernet/cavium/thunder/thunder
From: Sunil Goutham
This patch changes the way VF's irqs are visible in /proc/interrupts.
Instead of VF id, logical interface's netdev name is used for IRQ
naming and also all secondary VF's interrupts in multiqset config
use primary VF's netdev name.
Signed-off-by: Sunil Goutham
---
drivers/n
From: Sunil Goutham
88xx has 128 VFs, 81xx has 8 VFs and 83xx will have 32VFs.
Made changes to PF driver such that mailbox interrupt enable
registers are configuired based on number of VFs HW supports.
Also cleanedup mailbox irq handler registration code.
Signed-off-by: Sunil Goutham
---
drive
On Fri, Jul 08, 2016 at 09:28:03AM -0700, Tim Chen wrote:
>
> From: Tim Chen
> Subject: [PATCH] crypto: Cleanup sha multi-buffer code to use || instead of |
> for condition comparison and cleanup multiline comment style
>
> In sha*_ctx_mgr_submit, we currently use the | operator instead of ||
>
From: Suravee Suthikulpanit
CHANGES FROM V2
===
* Introduce struct irte_ops to avoid redundant "if/else" logics
for handling different IRTE formats. (patch 3 and 4)
(per Joerg's suggestion)
* Introduce proper #defines for a few magic numbers.
(per Joerg's suggestion)
From: Suravee Suthikulpanit
Move existing unions and structs for accessing/managing IRTE to a proper
header file. This is mainly to simplify variable declarations in subsequent
patches.
Besides, this patch also introduces new struct irte_ga for the new
128-bit IRTE format.
Signed-off-by: Surave
From: Suravee Suthikulpanit
This patch implements irq_set_vcpu_affinity() function to set up interrupt
remapping table entry with vapic mode for pass-through devices.
In case requirements for vapic mode are not met, it falls back to set up
the IRTE in legacy mode.
Signed-off-by: Suravee Suthiku
From: Suravee Suthikulpanit
This patch implements update_pi_irte function hook to allow SVM
communicate to IOMMU driver regarding how to set up IRTE for handling
posted interrupt.
In case AVIC is enabled, during vcpu_load/unload, SVM needs to update
IOMMU IRTE with appropriate host physical APIC
From: Suravee Suthikulpanit
Introduces a new IOMMU API, amd_iommu_update_ga(), which allows
KVM (SVM) to update existing posted interrupt IOMMU IRTE when
load/unload vcpu.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd_iommu.c | 63 +
d
Hi,
We can use mprotect to set read only or read/write.
mprotect_fixup()
vma_set_page_prot()
vm_pgprot_modify()
vm_get_page_prot()
protection_map[vm_flags &
(VM_READ|VM_WRITE|VM_EXEC|VM_SHARED)]
The following code s
From: Suravee Suthikulpanit
This patch introduces avic_ga_log_notifier, which will be called
by IOMMU driver whenever it handles the Guest vAPIC (GA) log entry.
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/include/asm/kvm_host.h | 2 ++
arch/x86/kvm/svm.c | 60 ++
From: Suravee Suthikulpanit
Currently, IOMMU support two interrupt remapping table entry formats,
32-bit (legacy) and 128-bit (GA). The spec also implies that it might
support additional modes/formats in the future.
So, this patch introduces the new struct amd_irte_ops, which allows
the same cod
On 2016/7/11 15:43, Paolo Bonzini wrote:
On 11/07/2016 08:07, Yang Zhang wrote:
mutex_lock(&kvm->arch.apic_map_lock);
+kvm_for_each_vcpu(i, vcpu, kvm)
+if (kvm_apic_present(vcpu))
+max_id = max(max_id, kvm_apic_id(vcpu->arch.apic));
+
+new = kzalloc(sizeof(st
On Tue, Jul 5, 2016 at 1:34 PM, Jeff Layton wrote:
> On Thu, 2016-06-30 at 15:46 +0200, Andreas Gruenbacher wrote:
>> A richacl consists of an NFSv4 acl and an owner, group, and other mask.
>> These three masks correspond to the owner, group, and other file
>> permission bits, but they contain NFS
On Fri, May 13, 2016 at 01:09:37PM +0200, Guillermo Rodriguez wrote:
> When disabling a PWM channel, the PWM clock was being stopped
> immediately after writing to PWM_DIS. As a result, the disabling
> of the PWM channel did not complete properly, and the PWM output
> might be left at the wrong lev
Hi Andrew,
Will this fixes series be able to make it for 4.7 ?
--
Regards
Kieran
On 29/06/16 06:00, Jan Kiszka wrote:
> On 2016-06-28 17:22, Kieran Bingham wrote:
>> Hi Andrew,
>>
>> Please consider this series for integration into the current rc series.
>> I had hoped to get this to you, with
On Wed, Jun 22, 2016 at 06:03:17PM +0100, Morten Rasmussen wrote:
> @@ -6905,11 +6906,19 @@ static int build_sched_domains(const struct cpumask
> *cpu_map,
> /* Attach the domains */
> rcu_read_lock();
> for_each_cpu(i, cpu_map) {
> + rq = cpu_rq(i);
> s
On Sun, 2016-03-07 at 20:31:53 UTC, Paul Gortmaker wrote:
> The Kconfig/Makefile currently controlling compilation of this code is:
>
> drivers/misc/cxl/Kconfig:config CXL_BASE
> drivers/misc/cxl/Kconfig: bool
>
> drivers/misc/cxl/Makefile:obj-$(CONFIG_CXL_BASE) += base.o
>
> ...m
On Wed, 2016-15-06 at 20:26:41 UTC, Greg Kurz wrote:
> A strange behaviour is observed when comparing PCI hotplug in QEMU, between
> x86 and pseries. If you consider the following steps:
> - start a VM
> - add a PCI device via the QEMU monitor before the rtasd has started (for
> example starting
On 2016/7/8 22:46, Jiri Olsa wrote:
On Wed, Jul 06, 2016 at 08:16:52PM +0800, Wangnan (F) wrote:
On 2016/7/6 19:36, Jiri Olsa wrote:
On Mon, Jul 04, 2016 at 06:20:03AM +, Wang Nan wrote:
SNIP
+struct perf_evlist *perf_evlist__new_aux(struct perf_evlist *parent)
+{
+ struct perf_
[Please don't top-post]
On 11/07/16 10:33, Bharat Kumar Gogada wrote:
> Hi Marc,
>
> Thanks for the reply.
>
> From PCIe Spec:
> MSI Enable Bit:
> If 1 and the MSI-X Enable bit in the MSI-X Message
> Control register (see Section 6.8.2.3) is 0, the
> function is permitted to use MSI to request s
On Monday, July 11, 2016 5:07:01 PM CEST Wan Zongshun wrote:
>
> On 2016年07月11日 16:03, Arnd Bergmann wrote:
> > On Sunday, July 10, 2016 3:27:26 PM CEST Wan Zongshun wrote:
> >> + ret = of_property_read_string(np, "compatible",
> >> &soc_dev_attr->soc_id);
> >> + if (ret)
> >>
On Monday 11 July 2016 02:49 PM, prahlad venkata wrote:
> On Mon, Jul 11, 2016 at 2:45 PM, Vignesh R wrote:
[...]
diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
index 29ea8d2..6c61f54 100644
--- a/drivers/spi/spi-ti-qspi.c
+++ b/drivers/spi
On Wed 06-07-16 11:28:42, Viresh Kumar wrote:
> On 01-07-16, 12:22, Tejun Heo wrote:
> I enabled traces with '-e all' to look at everything happening on the
> CPU.
>
> Following is what starts in the middle of the delayed-work handler:
>
> kworker/0:1H-40[000] d..1 2994.918766: console:
2016-07-11 18:24 GMT+08:00 Arnd Bergmann :
> On Monday, July 11, 2016 5:07:01 PM CEST Wan Zongshun wrote:
>>
>> On 2016年07月11日 16:03, Arnd Bergmann wrote:
>> > On Sunday, July 10, 2016 3:27:26 PM CEST Wan Zongshun wrote:
>> >> + ret = of_property_read_string(np, "compatible",
>> >> &soc_dev_
On Mon, Jul 11, 2016 at 11:57 AM, Andrey Ryabinin
wrote:
>
>
> On 07/10/2016 03:47 PM, Andy Lutomirski wrote:
>> Hi all-
>>
>> I found two nasty issues with virtually mapped stacks if KASAN is
>> enabled. The first issue is a crash: the first non-init stack is
>> allocated and accessed before KAS
Hi , Ingo
On Fri, 2016-07-08 at 09:38 +0200, Ingo Molnar wrote:
> * Eric W. Biederman wrote:
>
> > Sigh. Can we please just do the work to rip out the apic shutdown code
> > from the
> > kexec on panic code path?
> >
> > I forgetting details but the only reason we have do any apic shutdown i
On Mon, Jul 11, 2016 at 12:22:38PM +0530, Yendapally Reddy Dhananjaya Reddy
wrote:
> Hi Thierry,
>
> On Fri, Jul 8, 2016 at 8:46 PM, Thierry Reding
> wrote:
> > On Tue, Jul 05, 2016 at 02:00:25AM -0400, Yendapally Reddy Dhananjaya Reddy
> > wrote:
> >> Add support for the PWM controller presen
From: Fenghua Yu
This patch set introduces cache id to identify a cache in platform. It can
be useful in such areas as Cach Allocation Technology (CAT) where user
needs to specify how much cache is allocated on which cache. Cache id
provides a concise way to identify the cache. CAT patches will b
From: Fenghua Yu
Add an ABI document entry for /sys/devices/system/cpu/cpu*/cache/index*/id.
Signed-off-by: Fenghua Yu
Acked-by: Borislav Petkov
---
Documentation/ABI/testing/sysfs-devices-system-cpu | 17 +
1 file changed, 17 insertions(+)
diff --git a/Documentation/ABI/test
From: Fenghua Yu
Enable cache id in x86. Cache id comes from APIC ID and CPUID4.
Signed-off-by: Fenghua Yu
Acked-by: Borislav Petkov
---
arch/x86/kernel/cpu/intel_cacheinfo.c | 20
1 file changed, 20 insertions(+)
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c
b/arc
On Sun, Jul 10, 2016 at 11:48:11AM -0700, Stephane Eranian wrote:
> So we either redirect ref-cycles towards 0x013c
> (cpu_clk_unhalted:xlck) or another event maybe
Another solution is us introducing (another) fake event, say 0x0400,
which will have a constrained mask of: 0x0F | (6 << 32) and vari
On Monday, July 11, 2016 6:28:57 PM CEST Wan ZongShun wrote:
> 2016-07-11 18:24 GMT+08:00 Arnd Bergmann :
> > On Monday, July 11, 2016 5:07:01 PM CEST Wan Zongshun wrote:
> >>
> >> On 2016年07月11日 16:03, Arnd Bergmann wrote:
> >> > On Sunday, July 10, 2016 3:27:26 PM CEST Wan Zongshun wrote:
> >> >>
tree: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git WIP.hotplug
head: 0e5de16e9e45b4d853a31761fd74ff56998169a1
commit: 6b808294c6cbb28925fee0fedceb23196efbc367 [9/66] perf/x86: Convert the
core to the hotplug state machine
config: x86_64-allyesconfig (attached as .config)
compile
On Mon, Jul 11, 2016 at 12:06:29PM +0200, Thierry Reding wrote:
> On Mon, Jul 11, 2016 at 11:56:23AM +0200, Thierry Reding wrote:
> > On Tue, May 03, 2016 at 10:56:50AM -0500, Franklin S Cooper Jr wrote:
> > > Replace unit address from 0 to the proper physical address. Also insure
> > > that the un
On 04/07/16 10:38, Peng Fan wrote:
> Use devm_request_irq to simplify error handling path,
> when probe smmu device.
>
> Also devm_{request|free}_irq when init or destroy domain context.
>
> Signed-off-by: Peng Fan
> Cc: Will Deacon
> Cc: Robin Murphy
> ---
[...]
> @@ -2050,7 +2046,7 @@ static
On 2016/7/11 17:17, Paolo Bonzini wrote:
On 11/07/2016 10:56, Yang Zhang wrote:
On 2016/7/11 15:44, Paolo Bonzini wrote:
On 11/07/2016 08:06, Yang Zhang wrote:
Changes to MSI addresses follow the format used by interrupt remapping
unit.
The upper address word, that used to be 0, contains u
From: Fenghua Yu
Each cache is described by cacheinfo and is unique in the same index
across the platform. But there is no id for a cache. We introduce cache
ID to identify a cache.
Intel Cache Allocation Technology (CAT) allows some control on the
allocation policy within each cache that it con
On Mon, Jul 11, 2016 at 12:04:49PM +0200, Peter Zijlstra wrote:
> On Wed, Jun 22, 2016 at 06:03:16PM +0100, Morten Rasmussen wrote:
> > Systems with the SD_ASYM_CPUCAPACITY flag set indicate that sched_groups
> > at this level or below do not include cpus of all capacities available
> > (e.g. group
Aufmerksamkeit;
Hiermit teilen wir Ihnen mit, dass als privates Unternehmen, Kredite
Unternehmen mit Sitz in Großbritannien (Um Financial Ltd). Wir geben Kredite in
Höhe von $ 10.000 bis $ 300.000.000 bei 2% Zinssatz für alle Interessierten.
Land ist kein Hindernis, so fühlen sich frei, mit uns
On Mon, Jul 11, 2016 at 11:32:55AM +0100, Robin Murphy wrote:
> On 04/07/16 10:38, Peng Fan wrote:
> > Use devm_request_irq to simplify error handling path,
> > when probe smmu device.
> >
> > Also devm_{request|free}_irq when init or destroy domain context.
> >
> > Signed-off-by: Peng Fan
> > C
On Sun, Jul 10, 2016 at 05:47:37AM +0200, Christoph Hellwig wrote:
> On Wed, Jul 06, 2016 at 10:05:45AM +0200, Alexander Gordeev wrote:
> > > + pci_enable_msi, pci_enable_msi_range, pci_enable_msi_exact,
> > > pci_disable_msi,
> > > + pci_msi_vec_count, pci_enable_msix_range, pci_enable_msix_exact
On 11/07/2016 12:33, Yang Zhang wrote:
> On 2016/7/11 17:17, Paolo Bonzini wrote:
>> On 11/07/2016 10:56, Yang Zhang wrote:
>>> On 2016/7/11 15:44, Paolo Bonzini wrote:
On 11/07/2016 08:06, Yang Zhang wrote:
If interrupt remapping is on, KVM_CAP_X2APIC_API is needed even with 8
VCP
Hi,
[auto build test ERROR on ia64/next]
[also build test ERROR on v4.7-rc7 next-20160711]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Alexey-Dobriyan/kbuild-simpler-generation-of-assembly
On Mon, Jul 11, 2016 at 11:55:23AM +0200, Peter Zijlstra wrote:
> On Wed, Jun 22, 2016 at 06:03:15PM +0100, Morten Rasmussen wrote:
> > Add a topology flag to the sched_domain hierarchy indicating
> > sched_groups at this sched_domain level having different per cpu
> > capacity (e.g. big.LITTLE big
On Fri, Jul 08, 2016 at 05:29:11PM +0100, Eric Engestrom wrote:
> Signed-off-by: Eric Engestrom
> ---
>
> This can't compile without this macro… Is this header really used by anyone?
> Should it be removed, to avoid bit-rot?
Probably better to define something like:
#define SCTP_BITMAP_LEN
Ping!!
> -Original Message-
> From: Nava kishore Manne
> Sent: Monday, June 27, 2016 6:18 PM
> To: 'Rob Herring'
> Cc: pawel.m...@arm.com; mark.rutl...@arm.com;
> ijc+devicet...@hellion.org.uk; ga...@codeaurora.org; Michal Simek
> ; Soren Brinkmann ;
> ba...@ti.com; gre...@linuxfoundation
From: Suravee Suthikulpanit
This patch introduces a new IOMMU driver parameter, amd_iommu_guest_ir,
which can be used to specify different interrupt remapping mode for
passthrough devices to VM guest:
* legacy: Legacy interrupt remapping (w/ 32-bit IRTE)
* vapic : Guest vAPIC interrupt re
From: Suravee Suthikulpanit
This patch enables support for the new 128-bit IOMMU IRTE format,
which can be used for both legacy and vapic interrupt remapping modes.
It replaces the existing operations on IRTE, which can only support
the older 32-bit IRTE format, with calls to the new struct amd_i
From: Suravee Suthikulpanit
This patch adds support to detect and initialize IOMMU Guest vAPIC log
(GALOG). By default, it also enable GALog interrupt to notify IOMMU driver
when GA Log entry is created.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd_iommu_init.c | 112 +++
From: Suravee Suthikulpanit
Introduce struct iommu_dev_data.use_vapic flag, which IOMMU driver
uses to determine if it should enable vAPIC support, by setting
the ga_mode bit in the device's interrupt remapping table entry.
Currently, it is enabled for all pass-through device if vAPIC mode
is en
From: Suravee Suthikulpanit
This patch adds AMD IOMMU guest virtual APIC log (GALOG) handler.
When IOMMU hardware receives an interrupt targeting a blocking vcpu,
it creates an entry in the GALOG, and generates an interrupt to notify
the AMD IOMMU driver.
At this point, the driver processes the
On Fri, Jul 08, 2016 at 09:55:14AM +0200, Jiri Olsa wrote:
> On Thu, Jul 07, 2016 at 05:04:34PM +0100, Mark Rutland wrote:
> > + if (!cpu_map__has(evsel->cpus, evlist_cpu))
> > + continue;
> > +
> > + cpu = cpu_map__idx(evsel->cpus, evlist_cpu);
>
> you basica
Some PLLs can support dynamic reprogramming, which means just a L value
change is whats needed to change the PLL frequency without having to
explicitly enable/disable or bypass/re-lock the PLL.
Add support for such PLLs' initial configuration and the ops needed to
support the dynamic reprogramming
> > Hi Marc,
> >
> > Thanks for the reply.
> >
> > From PCIe Spec:
> > MSI Enable Bit:
> > If 1 and the MSI-X Enable bit in the MSI-X Message
> > Control register (see Section 6.8.2.3) is 0, the
> > function is permitted to use MSI to request service
> > and is prohibited from using its INTx# pin.
Some PLLs can have an additional early output (apart from
the main and aux outputs). Add support for the PLL driver
so it can be used to initialize/configure the early output
Signed-off-by: Rajendra Nayak
---
drivers/clk/qcom/clk-pll.c | 2 ++
drivers/clk/qcom/clk-pll.h | 1 +
2 files changed, 3
index is of type u8 in all places except in clk_hw_get_parent_by_index()
and return value of all round_rate functions is long except for
clk_hw_round_rate(). Make them consistent with the rest of the places
Signed-off-by: Rajendra Nayak
---
drivers/clk/clk.c| 4 ++--
include/linux/cl
Add a function to do initial configuration of the alpha plls
Signed-off-by: Rajendra Nayak
---
drivers/clk/qcom/clk-alpha-pll.c | 23 +++
drivers/clk/qcom/clk-alpha-pll.h | 13 +
2 files changed, 36 insertions(+)
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/dr
Am Freitag, den 08.07.2016, 19:30 +0900 schrieb Masahiro Yamada:
> The difference between with/without _optional variants is WARN_ON(1)
> when CONFIG_RESET_CONTROLLER is not defined.
>
> Signed-off-by: Masahiro Yamada
Applied, thank you.
regards
Philipp
Hi,
This series adds some additional support to the clk-alpha-pll and the
clk-pll drivers in preperation to add the CPU clock driver support
on msm8996
regards,
Rajendra
Rajendra Nayak (6):
clk: Fix inconsistencies in usage of data types
clk: qcom: Add support for alpha pll hwfsm ops
clk:
Some PLLs can support an alpha mode, and a single alpha
register (instead of registers to program the M/N values),
the contents of which depend on the alpha mode selected.
(They are either treated as two's complement or M/N value)
Add support for this in the clk PLL driver.
Signed-off-by: Rajendra
Add support to enable/disable the alpha pll using hwfsm
Signed-off-by: Rajendra Nayak
---
drivers/clk/qcom/clk-alpha-pll.c | 109 ++-
drivers/clk/qcom/clk-alpha-pll.h | 1 +
2 files changed, 98 insertions(+), 12 deletions(-)
diff --git a/drivers/clk/qcom/cl
On Jul 08 2016 or thereabouts, Bastien Nocera wrote:
> On Wed, 2016-06-29 at 19:28 +1000, Peter Hutterer wrote:
> > +static int hidpp_battery_get_property(struct power_supply *psy,
> > + enum power_supply_property psp,
> > + un
On Tue, Mar 29, 2016 at 08:55:45PM +0200, Paul Kocialkowski wrote:
> The current TWL6030 code for the TWL PWM driver does not reliably disable the
> PWM output, as tested with LEDs. The previous commit to that driver introduced
> that regression.
>
> However, it does make sense to disable the PWM
Hi,
[auto build test ERROR on ia64/next]
[also build test ERROR on v4.7-rc7 next-20160711]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Alexey-Dobriyan/kbuild-simpler-generation-of-assembly
Hi,
[auto build test ERROR on ia64/next]
[also build test ERROR on v4.7-rc7 next-20160711]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Alexey-Dobriyan/kbuild-simpler-generation-of-assembly
On Mon, 2016-07-11 at 03:20 +, Zheng, Lv wrote:
>
> > This worries me as there is no plan after "During the period the
> > userspace hasn't been switched to use the new event".
> >
> > I really hope you'll keep sending SW_LID for reliable LID
> > platforms,
> > and not remove it entirely as
On 09.07.2016 00:19, Alexey Khoroshilov wrote:
If adp5520_bl_setup() fails, sysfs group left unremoved.
By the way, fix overcomplicated assignement of error code.
Found by Linux Driver Verification project (linuxtesting.org).
Signed-off-by: Alexey Khoroshilov
Acked-by: Michael Hennerich
On Fri, Jul 8, 2016 at 8:58 PM, Hugh Dickins wrote:
> Hi Dmitry,
>
> On Tue, 5 Jul 2016, Kirill A. Shutemov wrote:
>> On Mon, Jul 04, 2016 at 04:10:53PM -0700, Hugh Dickins wrote:
>> > On Fri, 1 Jul 2016, Dmitry Vyukov wrote:
>> > > Hello,
>> > >
>> > > I am getting the following crashes while run
On Jul 08 2016 or thereabouts, Bastien Nocera wrote:
> On Fri, 2016-07-08 at 16:35 +0200, Bastien Nocera wrote:
> > On Wed, 2016-06-29 at 19:28 +1000, Peter Hutterer wrote:
> > > +static int hidpp_battery_get_property(struct power_supply *psy,
> > > + enum power_
On Mon, 2016-07-11 at 09:23 +0200, Michal Hocko wrote:
> On Fri 08-07-16 10:27:38, Jeff Layton wrote:
> > On Fri, 2016-07-08 at 16:23 +0200, Michal Hocko wrote:
> > > On Fri 08-07-16 08:51:54, Jeff Layton wrote:
> > > >
> > > > On Fri, 2016-07-08 at 14:22 +0200, Michal Hocko wrote:
> > > [...]
> >
On Mon, Jul 11, 2016 at 11:37:18AM +0100, Morten Rasmussen wrote:
> On Mon, Jul 11, 2016 at 12:04:49PM +0200, Peter Zijlstra wrote:
> > On Wed, Jun 22, 2016 at 06:03:16PM +0100, Morten Rasmussen wrote:
> > > Systems with the SD_ASYM_CPUCAPACITY flag set indicate that sched_groups
> > > at this leve
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