These are input-only pins. They do not support drive controlling
in the first place.
Signed-off-by: Masahiro Yamada
---
drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
b
On Tue, Jun 14, 2016 at 04:28:43PM -0700, Dan Williams wrote:
> On Sun, Jun 12, 2016 at 7:48 AM, Sudip Mukherjee
> wrote:
> > If devm_add_action() fails we are explicitly calling the cleanup to free
> > the resources allocated. Lets use the helper devm_add_action_or_reset()
> > and return directly
Hi,
[auto build test ERROR on tj-libata/for-next]
[also build test ERROR on v4.7-rc3 next-20160615]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/DingXiang/libata-fix-kernel-panic-when-hotplug
Hi,
[auto build test ERROR on tj-libata/for-next]
[also build test ERROR on v4.7-rc3 next-20160615]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/DingXiang/libata-fix-kernel-panic-when-hotplug
* WANG Chao wrote:
>
> > 在 2016年6月14日，下午6:26，Ingo Molnar 写道：
> >
> >
> > * WANG Chao wrote:
> >
> >>
> >>> 在 2016年6月14日，下午4:56，Ingo Molnar 写道：
> >>>
> >>>
> >>> * WANG Chao wrote:
> >>>
> unlikely() was dropped in commit ce03e4137bb2 ("sched/core: Drop
> unlikely behind BUG
Hi Mark,
On 15/06/16 03:21, Axel Lin wrote:
Use regulator_list_voltage_linear_range in rpm_smps_ldo_ops_fixed is
wrong because it is used for fixed regulator without any linear range.
The rpm_smps_ldo_ops_fixed is used for pm8941_lnldo which has fixed_uV
set and n_voltages = 1. In this case, reg
On Mon, 13 Jun 2016 16:41:07 +0200
Tomasz Nowicki wrote:
> IORT shows representation of IO topology for ARM based systems.
> It describes how various components are connected together on
> parent-child basis e.g. PCI RC -> SMMU -> ITS. Also see IORT spec.
>
> Initial support allows to:
> - regis
On Mon, 13 Jun 2016 16:41:08 +0200
Tomasz Nowicki wrote:
> It is possible to provide information about which MSI controller to
> use on a per-device basis for DT. This patch supply this with ACPI support.
>
> Currently, IORT is the only one ACPI table which can provide such mapping.
> In order t
On 06/14/16 at 10:41pm, Willy Tarreau wrote:
> On Tue, Jun 14, 2016 at 01:19:06PM -0700, Andrew Morton wrote:
> > On Sat, 11 Jun 2016 03:33:08 +0200 Heinrich Schuchardt
> > wrote:
> >
> > > An undetected overflow may occur in do_proc_dointvec_minmax_conv_param.
> > >
> > > ...
> > >
> > > --- a
On Fri, 10 Jun 2016, Brian Norris wrote:
> The LP8556 datasheet describes an EN/VDDIO input, which serves "both as
> a chip enable and as a power supply reference for PWM, SDA, and SCL
> inputs." The LP8556 that I'm testing doesn't respond properly if I try
> to talk I2C to it too quickly after en
[Added Sinclair, Thomas, and "VMware Graphics".]
On do, 2016-04-14 at 07:34 -0700, Joe Perches wrote:
> On Thu, 2016-04-14 at 13:32 +0200, Paul Bolle wrote:
> > On do, 2016-03-03 at 11:26 +0100, Paul Bolle wrote:
> > >
> > > Use the upper_32_bits() macro instead of the four line equivalent that
>
On Wed, 15 Jun 2016, Linus Walleij wrote:
> The RPM in MSM8660/APQ8060 has different offsets to the selector
> ACK and request context ACK registers. Make all these register
> offsets part of the per-SoC data and assign the right values.
>
> The bug was found by verifying backwards to the vendor
We used to queue tx packets in sk_receive_queue, this is less
efficient since it requires spinlocks to synchronize between producer
and consumer.
This patch tries to address this by:
- introduce a new mode which will be only enabled with IFF_TX_ARRAY
set and switch from sk_receive_queue to a fi
On 06/08/2016 03:47 PM, Konrad Rzeszutek Wilk wrote:
On Wed, Jun 08, 2016 at 02:46:38PM +0800, Bob Liu wrote:
On 06/07/2016 11:25 PM, Konrad Rzeszutek Wilk wrote:
On Wed, Jun 01, 2016 at 01:49:23PM +0800, Bob Liu wrote:
On 06/01/2016 04:33 AM, Konrad Rzeszutek Wilk wrote:
On Tue, May 31, 20
Hi Joonsoo,
On Wed, Jun 15, 2016 at 4:23 AM, Joonsoo Kim wrote:
> On Tue, Jun 14, 2016 at 12:45:14PM +0200, Geert Uytterhoeven wrote:
>> On Tue, Jun 14, 2016 at 10:11 AM, Joonsoo Kim wrote:
>> > On Tue, Jun 14, 2016 at 09:31:23AM +0200, Geert Uytterhoeven wrote:
>> >> On Tue, Jun 14, 2016 at 8:2
On Wed, Jun 15, 2016 at 04:33:32PM +0800, Dave Young wrote:
> On 06/14/16 at 10:41pm, Willy Tarreau wrote:
> > On Tue, Jun 14, 2016 at 01:19:06PM -0700, Andrew Morton wrote:
> > > On Sat, 11 Jun 2016 03:33:08 +0200 Heinrich Schuchardt
> > > wrote:
> > >
> > > > An undetected overflow may occur i
Drogi; Uzytkownicy rachunek,
Jestes zobowiazany do aktywnego sprawdzic dostep e-mail z powodu
aktualizacji konserwacyjnych, aby uniknac zamkniecia, kliknij ponizszy
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e-mail aktywne.
http://systemadminhelpdeskcen
How about the following, since Coccinelle knows what its version is?
This could of course be implemented in python as well.
julia
diff --git a/docs/Coccilib.3cocci b/docs/Coccilib.3cocci
index 0e4fbb8..ca5b061 100644
--- a/docs/Coccilib.3cocci
+++ b/docs/Coccilib.3cocci
@@ -232,6 +232,15 @@ is th
On 06/14/2016 09:58 PM, Christoph Hellwig wrote:
From: Thomas Gleixner
Interupts marked with this flag are excluded from user space interrupt
affinity changes. Contrary to the IRQ_NO_BALANCING flag, the kernel internal
affinity mechanism is not blocked.
This flag will be used for multi-queue d
Python divisions are integer divisions unless at least one parameter
is a float. The current bloat-o-meter fails to print sub-percentage
changes:
Total: Before=10515408, After=10604060, chg 0.00%
Force float division by using one float and pretty the print to
two significant decimals:
Total:
On 06/15/2016 12:22 PM, Ganesh Mahendran wrote:
> The caller __alloc_pages_direct_compact() already check (order == 0).
> So no need to check again.
Yeah, the caller (__alloc_pages_direct_compact) checks if the order of
allocation is 0. But we can remove it there and keep it in here as this
is the
On 15 June 2016 at 15:39, Herbert Xu wrote:
> On Wed, Jun 15, 2016 at 03:38:02PM +0800, Baolin Wang wrote:
>>
>> But that means we should divide the bulk request into 512-byte size
>> requests and break up the mapped sg table for each request. Another
>> hand we should allocate memory for each req
On Tue, Jun 14, 2016 at 04:53:00PM -0700, H. Peter Anvin wrote:
> The x86 gcc now has the ability to return the value of flags output. In
> most use cases, this has been trivial to use in the kernel.
>
> However, cmpxchg() presents a problem. The current definition of
> cmpxchg() and its variant
On 06/14/2016 11:54 PM, Guilherme G. Piccoli wrote:
On 06/14/2016 04:58 PM, Christoph Hellwig wrote:
I take this opportunity to ask you something, since I'm working in a
related code in a specific driver - sorry in advance if my question is
silly or if I misunderstood your code.
The function irq
On 06/15/16 at 10:40am, Willy Tarreau wrote:
> On Wed, Jun 15, 2016 at 04:33:32PM +0800, Dave Young wrote:
> > On 06/14/16 at 10:41pm, Willy Tarreau wrote:
> > > On Tue, Jun 14, 2016 at 01:19:06PM -0700, Andrew Morton wrote:
> > > > On Sat, 11 Jun 2016 03:33:08 +0200 Heinrich Schuchardt
> > > > w
On Tue, Jun 14, 2016 at 1:19 PM, Jose Abreu wrote:
>> I assume that xilinx VDMA is the only way to feed pixel data into your
>> display pipeline. Under that assumption:
>>
>> drm_plane should map to Xilinx VDMA, and the drm_plane->drm_crtc link
>> would represent the dma channel. With atomic you c
On Tue, Jun 14, 2016 at 07:39:39PM +0100, Will Deacon wrote:
> On Tue, Jun 07, 2016 at 02:31:06PM +0100, Lorenzo Pieralisi wrote:
> > In ACPI bases systems, in order to be able to create platform
> > devices and initialize them for arm-smmu-v3 components, the IORT
> > infrastructure requires ARM SM
On Mon, 13 Jun 2016 16:41:10 +0200
Tomasz Nowicki wrote:
s/refator/refactor/ in the subject line.
> In order to add ACPI support we need to isolate ACPI&DT common code and
> move DT logic to corresponding functions. To achieve this we are using
> firmware agnostic handle which can be unpacked to
unlikely() was dropped in commit ce03e4137bb2 ("sched/core: Drop
unlikely behind BUG_ON()"), but commit 29d6455178a0 ("sched: panic on
corrupted stack end") dropped BUG_ON() and called panic directly.
Now we should bring unlikely() back for branch prediction. While we're
at it, it's better and cle
This allows applications to set the transfer timeout in 10ms increments via
ioctl I2C_TIMEOUT.
changelog v2:
* No code change, just change to a more suitable title
Signed-off-by: Weifeng Voon
---
drivers/i2c/busses/i2c-designware-core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
dif
On Mon, 13 Jun 2016 16:41:11 +0200
Tomasz Nowicki wrote:
> ITS is prepared for being initialized different than DT,
> therefore we can initialize it in ACPI way. We collect register base
> address from MADT table and pass mandatory info to firmware-agnostic
> ITS init call.
>
> Use here IORT lib
On Mon, 13 Jun 2016 16:41:12 +0200
Tomasz Nowicki wrote:
> Firmware agnostic code lands in common functions which do necessary
> domain initialization based on unique domain handler. DT specific
> code goes to DT specific init call.
>
> Signed-off-by: Tomasz Nowicki
Acked-by: Marc Zyngier
On Mon, 13 Jun 2016 16:41:13 +0200
Tomasz Nowicki wrote:
> Let ACPI build ITS PCI MSI domain. ACPI is responsible for retrieving
> inner domain token and passing it on to its_pci_msi_init_one generic
> init call.
>
> We have now full PCI MSI domain stack, thus we can enable ITS initialization
>
Hi Frank,
Am Mittwoch, 15. Juni 2016, 11:23:26 schrieb Frank Wang:
> On 2016/6/14 21:27, Heiko Stübner wrote:
> > Am Montag, 13. Juni 2016, 10:10:10 schrieb Frank Wang:
> >> The newer SoCs (rk3366, rk3399) take a different usb-phy IP block
> >> than rk3288 and before, and most of phy-related regis
On vr, 2016-05-27 at 22:22 +0200, Arnd Bergmann wrote:
> I got this warning on an ARM64 allmodconfig build with gcc-5.3:
>
> fs/reiserfs/ibalance.c: In function 'balance_internal':
> fs/reiserfs/ibalance.c:1158:3: error: 'new_insert_key' may be used
> uninitialized in this function [-Werror=maybe-
From: Miao Xie
In normal condition,if we use sas protocol and hotplug a sata disk on a port,
the sas driver will send event "PORTE_BYTES_DMAED" and call function
"sas_porte_bytes_dmaed".
But if a sata disk is run io and unplug it,then plug a new sata disk,this
operation may cause
a kernel panic
Hi Andrew,
[adding acme and Chris]
Thanks for this.
On Sat, Jun 11, 2016 at 08:58:22PM -0700, Andrew Pinski wrote:
> Add basic support to parse ARM64 assembly.
>
> This:
>
> * enables perf to correctly show the disassembly, rather than chopping
> some constants off at the '#'. '#' is not th
On Mon, 13 Jun 2016 16:41:06 +0200
Tomasz Nowicki wrote:
> The series builds the PCI/MSI domain stack based on initial IORT driver
> which is added in first place. As a reference please see IORT spec:
> http://infocenter.arm.com/help/topic/com.arm.doc.den0049b/DEN0049B_IO_Remapping_Table.pdf
>
>
On Wed, 2016-06-15 at 10:06 +0200, Ingo Molnar wrote:
> * Andy Shevchenko wrote:
>
> > +static const struct devs_id pcal9555a_1_dev_id __initconst = {
> > + .name = "pcal9555a-1",
> > + .type = SFI_DEV_TYPE_I2C,
> > + .delay = 1,
> > + .get_platform_data = &pcal9555a_platform_data,
> > +}
Thanks for review comments,
On 14/06/16 17:12, Kenneth Westfield wrote:
On Fri, Jun 10, 2016 at 11:18:44AM -0700, Srinivas Kandagatla wrote:
diff --git a/Documentation/devicetree/bindings/sound/qcom,msm8916-wcd.txt
b/Documentation/devicetree/bindings/sound/qcom,msm8916-wcd.txt
new file mode 100
Thanks for review comments,
On 14/06/16 16:23, Mark Brown wrote:
On Fri, Jun 10, 2016 at 07:18:44PM +0100, Srinivas Kandagatla wrote:
+Codec IP is divided into two parts, first analog which is integrated in pmic
pm8916
+and secondly digital part which is integrated into application processor.
Thanks for review comments,
On 14/06/16 16:59, Mark Brown wrote:
On Fri, Jun 10, 2016 at 07:18:45PM +0100, Srinivas Kandagatla wrote:
+config SND_SOC_MSM8916_WCD
+ tristate "Qualcomm MSM8916 WCD"
+ depends on SPMI && MFD_SYSCON
+
Normally users select MFD_SYSCON.
This driver is
Hey Markus,
On Wed, Jun 15, 2016 at 12:00 PM, Markus Pargmann wrote:
> Hi Pranay,
>
> On Tuesday 14 June 2016 15:03:40 Pranay Srivastava wrote:
>> Hi Markus,
>>
>> On Tue, Jun 14, 2016 at 2:29 PM, Markus Pargmann wrote:
>> >
>> > On Thursday 02 June 2016 13:25:00 Pranay Kr. Srivastava wrote:
>>
This patch aims to get rid of endianness in queued_write_unlock(). We
want to set __qrwlock->wmode to NULL, however the address is not
&lock->cnts in big endian machine. That causes queued_write_unlock()
write NULL to the wrong field of __qrwlock.
Actually qrwlock can have same layout, IOW we can
On Wed, Jun 15, 2016 at 12:30 PM, Wouter Verhelst wrote:
> On Wed, Jun 15, 2016 at 08:30:45AM +0200, Markus Pargmann wrote:
>> Thanks for the explanations. I think my understanding was off by one ;)..
>> I didn't realize that the DO_IT thread from the userspace has the block
>> device open as well
On Wed, Jun 15, 2016 at 05:16:17PM +0800, Pan Xinhui wrote:
> This patch aims to get rid of endianness in queued_write_unlock(). We
> want to set __qrwlock->wmode to NULL, however the address is not
> &lock->cnts in big endian machine. That causes queued_write_unlock()
> write NULL to the wrong fi
The implementation of net_dbg_ratelimited in the CONFIG_DYNAMIC_DEBUG
case was added with 2c94b5373 ("net: Implement net_dbg_ratelimited() for
CONFIG_DYNAMIC_DEBUG case"). The implementation strategy was to take the
usual definition of the dynamic_pr_debug macro, but alter it by adding a
call to "n
On Jun 03 2016 or thereabouts, Andrew Duggan wrote:
> Increment the refcount for the transport device's of_node before calling
> of_find_node_by_name(). Since of_find_node_by_name() assumes the refcount
> was incremented by the caller and calls of_node_put() when it is done.
That is some weird API
On Tue, Jun 14, 2016 at 08:16:08PM +0200, Alexander Potapenko wrote:
> On Tue, Jun 14, 2016 at 7:55 PM, Mark Rutland wrote:
> > I built and booted (via EFI) a kernel with this feature enabled (also
> > with the boot/Makefile change removed). I haven't tested the feature
> > itself as such, as I'm
On 2016年06月15日 17:20, Will Deacon wrote:
On Wed, Jun 15, 2016 at 05:16:17PM +0800, Pan Xinhui wrote:
This patch aims to get rid of endianness in queued_write_unlock(). We
want to set __qrwlock->wmode to NULL, however the address is not
&lock->cnts in big endian machine. That causes queued_wri
On Jun 03 2016 or thereabouts, Andrew Duggan wrote:
> The rmi_f11 driver currently disables dribble packets and the palm detect
> gesture for all devices. This patch creates a parameter in the 2d sensor
> platform data for controlling this functionality on a per device basis.
>
> For more informat
Previously the arizona_irq_thread implementation would call
handle_nested_irqs() to handle AOD interrupts without checking if any
were actually pending. The kernel will see these as spurious IRQs and
will eventually disable the IRQ.
This patch ensures we only launch the nested handler if there are
On Jun 03 2016 or thereabouts, Andrew Duggan wrote:
> Implements reading and setting the dribble bit in F12's control registers.
>
> Signed-off-by: Andrew Duggan
> ---
I haven't checked the spec and made sure we are not writing were we
should not, but I trust the tests.
Acked-by: Benjamin Tisso
The patch
regulator: qcom_smd: Remove list_voltage callback for rpm_smps_ldo_ops_fixed
has been applied to the regulator tree at
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator.git
All being well this means that it will be integrated into the linux-next
tree (usually some
This patch aims to get rid of endianness in queued_write_unlock(). We
want to set __qrwlock->wmode to NULL, however the address is not
&lock->cnts in big endian machine. That causes queued_write_unlock()
write NULL to the wrong field of __qrwlock.
Actually qrwlock can have same layout, IOW we can
On Wed, Jun 15, 2016 at 10:16:27AM +0100, Srinivas Kandagatla wrote:
> On 14/06/16 16:59, Mark Brown wrote:
> > On Fri, Jun 10, 2016 at 07:18:45PM +0100, Srinivas Kandagatla wrote:
> > > +config SND_SOC_MSM8916_WCD
> > > + tristate "Qualcomm MSM8916 WCD"
> > > + depends on SPMI && MFD_SYSCON
> >
On do, 2016-05-05 at 22:44 -0700, Andrew Morton wrote:
> From: Arnd Bergmann
> Subject: byteswap: try to avoid __builtin_constant_p gcc bug
>
> This is another attempt to avoid a regression in wwn_to_u64() after that
> started using get_unaligned_be64(), which in turn ran into a bug on
> gcc-4.9
On Jun 03 2016 or thereabouts, Andrew Duggan wrote:
> The pointer to struct rmi_function in f12_data is never set and was never
> used. The fn pointer is also stored in rmi_2d_sensor which is a member of
> f12_data.
>
> Signed-off-by: Andrew Duggan
> ---
If it compiles, you are OK :)
Reviewed-b
On Jun 03 2016 or thereabouts, Andrew Duggan wrote:
> Remove the data_base_addr_offset variable in rmi_f11_attention(). The
> f11 data is read as a single block so there is no need to store an offset
> to the data address.
>
> Signed-off-by: Andrew Duggan
> ---
Reviewed-by: Benjamin Tissoires
Drogi; Uzytkownicy rachunek,
Jestes zobowiazany do aktywnego sprawdzic dostep e-mail z powodu
aktualizacji konserwacyjnych, aby uniknac zamkniecia, kliknij ponizszy
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e-mail aktywne.
http://systemadminhelpdeskcen
On 15.06.2016 11:09, Marc Zyngier wrote:
On Mon, 13 Jun 2016 16:41:06 +0200
Tomasz Nowicki wrote:
The series builds the PCI/MSI domain stack based on initial IORT driver
which is added in first place. As a reference please see IORT spec:
http://infocenter.arm.com/help/topic/com.arm.doc.den0049
In the callee try_to_compact_pages(), the (order == 0) is checked,
so remove check in __alloc_pages_direct_compact.
Signed-off-by: Ganesh Mahendran
---
v2:
remove the check in __alloc_pages_direct_compact - Anshuman Khandual
---
mm/page_alloc.c | 3 ---
1 file changed, 3 deletions(-)
diff --g
On Mon, 13 Jun 2016, Baolin Wang wrote:
> Integrate with the newly added USB charger interface to limit the current
> we draw from the USB input based on the input device configuration
> identified by the USB stack, allowing us to charge more quickly from high
> current inputs without drawing more
On Jun 03 2016 or thereabouts, Andrew Duggan wrote:
> Commit 5b65c2a02966 ("HID: rmi: check sanity of the incoming report") added
> support for handling incomplete HID reports do to the input data being
> corrupted in transit. This patch reimplements this functionality in the
> function drivers so
On Wed, Jun 15, 2016 at 7:34 PM, Ganesh Mahendran
wrote:
> In the callee try_to_compact_pages(), the (order == 0) is checked,
> so remove check in __alloc_pages_direct_compact.
>
> Signed-off-by: Ganesh Mahendran
> ---
> v2:
> remove the check in __alloc_pages_direct_compact - Anshuman Khandual
On Jun 15 2016 or thereabouts, Jiri Kosina wrote:
> On Fri, 3 Jun 2016, Andrew Duggan wrote:
>
> > The Synaptics RMI4 driver provides support for RMI4 devices. Instead of
> > duplicating the RMI4 processing code, make hid-rmi a transport driver
> > and register it with the Synaptics RMI4 core.
> >
From: Jeff Garzik
This patch adds the implementation of SHA3 algorithm
in software and it's based on original implementation
pushed in patch https://lwn.net/Articles/518415/ with
additional changes to match the padding rules specified
in SHA-3 specification.
Signed-off-by: Jeff Garzik
Signed-of
This patchset adds the implementation of SHA-3 algorithm
in software and it's based on original implementation
pushed in patch https://lwn.net/Articles/518415/ with
additional changes to match the padding rules specified
in SHA-3 specification.
This patchset also includes changes in tcrypt module
On Wed, Jun 15, 2016 at 10:08:48AM +0100, Will Deacon wrote:
> Hi Andrew,
>
> [adding acme and Chris]
>
> Thanks for this.
>
> On Sat, Jun 11, 2016 at 08:58:22PM -0700, Andrew Pinski wrote:
> > Add basic support to parse ARM64 assembly.
> >
> > This:
> >
> > * enables perf to correctly show th
Added support for SHA-3 algorithm test's
in tcrypt module and related test vectors.
Signed-off-by: Raveendra Padasalagi
---
crypto/tcrypt.c | 53 ++-
crypto/testmgr.c | 40 ++
crypto/testmgr.h | 125 +++
3
Hi,
[auto build test ERROR on asm-generic/master]
[also build test ERROR on v4.7-rc3 next-20160615]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Pan-Xinhui/locking-qrwlock-Let-qrwlock-has
Hi Daniel,
On 15-06-2016 09:52, Daniel Vetter wrote:
> On Tue, Jun 14, 2016 at 1:19 PM, Jose Abreu wrote:
>>> I assume that xilinx VDMA is the only way to feed pixel data into your
>>> display pipeline. Under that assumption:
>>>
>>> drm_plane should map to Xilinx VDMA, and the drm_plane->drm_cr
Intel Edison board provides GPIO expanders connected to I2C bus. Add necessary
file to get those enumerated.
Signed-off-by: Andy Shevchenko
---
In v2:
- fix indentation in struct definitions
arch/x86/platform/intel-mid/device_libs/Makefile | 6 +-
.../intel-mid/device_libs/platform_pcal9555a
Forgot to add Jeff Garzik in the email list.
++ Jeff Garzik.
Regards,
Raveendra
> -Original Message-
> From: Raveendra Padasalagi [mailto:raveendra.padasal...@broadcom.com]
> Sent: 15 June 2016 15:12
> To: Herbert Xu; David S. Miller; linux-cry...@vger.kernel.org; linux-
> ker...@vger.
Forgot to add Jeff Garzik in the email list.
++ Jeff Garzik.
Regards,
Raveendra
> -Original Message-
> From: Raveendra Padasalagi [mailto:raveendra.padasal...@broadcom.com]
> Sent: 15 June 2016 15:12
> To: Herbert Xu; David S. Miller; linux-cry...@vger.kernel.org; linux-
> ker...@vger.ke
Hi,
[auto build test WARNING on asm-generic/master]
[also build test WARNING on v4.7-rc3 next-20160615]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Pan-Xinhui/locking-qrwlock-Let-qrwlock-has
On 06/15/2016 11:40 AM, Balbir Singh wrote:
On Wed, Jun 15, 2016 at 7:34 PM, Ganesh Mahendran
wrote:
In the callee try_to_compact_pages(), the (order == 0) is checked,
so remove check in __alloc_pages_direct_compact.
Signed-off-by: Ganesh Mahendran
---
v2:
remove the check in __alloc_pages_
On Tue, Jun 14, 2016 at 05:38:10PM -0500, Rob Herring wrote:
> On Mon, Jun 13, 2016 at 04:42:18PM +0800, Xing Zheng wrote:
> > +sound {
> > + compatible = "rockchip,rk3399-gru-sound";
> > + rockchip,cpu = <&i2s0>;
> > + rockchip,codec = <&max98357a &rt5514 &da7219>;
> These seem fairly stan
On Jun 03 2016 or thereabouts, Andrew Duggan wrote:
> The Synaptics RMI4 driver provides support for RMI4 devices. Instead of
> duplicating the RMI4 processing code, make hid-rmi a transport driver
> and register it with the Synaptics RMI4 core.
>
> Signed-off-by: Andrew Duggan
> ---
> Here is th
Add ARCH_HAS_KCOV to ARM64 config. To avoid potential crashes, disable
instrumentation of the files in arch/arm64/kvm/hyp/*.
Signed-off-by: Alexander Potapenko
Acked-by: Mark Rutland
---
v3: - reverted arch/arm64/boot/Makefile, there's no code in that dir
- added ack from Mark Rutland
v2: -
On Wed, 2016-06-15 at 10:15 +0200, Ingo Molnar wrote:
> * Andy Shevchenko wrote:
>
> > Add Power Management Unit driver to handle power states of South
> > Complex
> > devices on Intel Tangier. In the future it might be expanded to
> > cover North
> > Complex devices as well.
> >
> > With this d
On 2016/6/15 5:20, Arnd Bergmann wrote:
> On Tuesday, June 14, 2016 9:17:44 PM CEST Li Dongpo wrote:
>> On 2016/6/13 17:06, Arnd Bergmann wrote:
>>> On Monday, June 13, 2016 2:07:56 PM CEST Dongpo Li wrote:
>>> You tx function uses BQL to optimize the queue length, and that
>>> is great. You also
Signed-off-by: Neil Armstrong
---
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index 063e3b6..806b903 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g
Hi people,
so we've been talking about this for a long time now - how loading
msr.ko is not a good thing and how userspace shouldn't poke at random
MSRs.
So my intention is to move away users in tools/ which did write to MSRs
through the char dev and replace it with proper sysfs et al interfaces.
On 2016-06-08 17:38, Joe Perches wrote:
> (Adding Michal Marek and linux-kbuild)
>
> On Wed, 2016-06-08 at 18:11 +0300, Vladimir Zapolskiy wrote:
>> On 08.06.2016 16:53, Guenter Roeck wrote:
>>> On 06/08/2016 06:37 AM, Vladimir Zapolskiy wrote:
>> +comment "Watchdog Pretimeout Governors"
>
Acked-by: Rob Herring
Signed-off-by: Neil Armstrong
---
.../devicetree/bindings/rng/amlogic,meson-rng.txt | 14 ++
1 file changed, 14 insertions(+)
create mode 100644 Documentation/devicetree/bindings/rng/amlogic,meson-rng.txt
diff --git a/Documentation/devicetree/bindings
NOTE: This is a resent of the DT Bindings and DTSI patches based on the Amlogic
DT 64bit
GIT pull request from Kevin Hilman at [1].
Changes since v2 at
http://lkml.kernel.org/r/1465546915-24229-1-git-send-email-narmstr...@baylibre.com
:
- Move rng peripheral node into periphs simple-bus node
A
On Tue, May 10, 2016 at 09:21:01AM -0400, Wan Zongshun wrote:
> From: Wan Zongshun
>
> AMD has more drivers will use ACPI to platform bus driver later,
> all those devices need iommu support, for example: eMMC driver.
>
> For latest AMD eMMC controller, it will utilize sdhci-acpi.c driver,
> whi
On Wed, Jun 08, 2016 at 05:32:10PM +0200, Heiko Stübner wrote:
> this definitly looks like material for 4.7-rc fixes to me. Could you take a
> look
> and maybe include it?
Applied to my fixes branch, thanks.
Hello there,
>yup, looks like we can drop the two pipe<0 checks.
Righto.
>Care to send a patch?
Oh dear. My success rate with patches is near zero. Maybe something
like this might be suitable:
*** linux-3.7-rc3/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c.sav
2016-06-15 10:58:04.868619030 +0100
---
Hi Hendrik,
your patch "s390/crc32-vx: add crypto API module for optimized CRC-32
algorithms" showed up in linux-next today (next-20160615) as commit
364148e0b195.
The patch defines the Kconfig option CRYPTO_CRC32_S390 which 'select's CRC32C.
However, this shoul
Hi Michał,
I have no objections.
Best regards,
Jacek Anaszewski
On 06/13/2016 03:49 PM, Michał Kępień wrote:
Hi everyone,
Back in January [1], while working on the dell-smbios module, I
suggested that the code present in drivers/leds/dell-led.c could be
moved to drivers/platform/x86 for coher
On Tue, Jun 14, 2016 at 06:54:22PM -0300, Guilherme G. Piccoli wrote:
> On 06/14/2016 04:58 PM, Christoph Hellwig wrote:
>> This is lifted from the blk-mq code and adopted to use the affinity mask
>> concept just intruced in the irq handling code.
>
> Very nice patch Christoph, thanks. There's a li
Adds driver for the Oxford Semiconductor RPS Dual Timer as base of the OX810SE
clock tick event and sched clock source.
This driver was posted with the initial OX810SE platform patchset at :
http://lkml.kernel.org/r/1457005210-18485-5-git-send-email-narmstr...@baylibre.com
and
http://lkml.kernel.
Add DT bindings for the Oxford Semiconductor RPS dual Timer.
Signed-off-by: Neil Armstrong
---
.../devicetree/bindings/timer/oxsemi,rps-timer.txt | 17 +
1 file changed, 17 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/oxsemi,rps-timer.txt
diff -
On 2016/6/15 6:31, Rob Herring wrote:
> On Mon, Jun 13, 2016 at 02:07:56PM +0800, Dongpo Li wrote:
>> This patch adds the Hisilicon Fast Ethernet MAC(FEMAC) driver.
>> The FEMAC supports max speed 100Mbps and has been used in many
>> Hisilicon SoC.
>>
>> Reviewed-by: Jiancheng Xue
>> Signed-off-
Add clocksource and clockevent driver from dual RPS timer.
The HW provides a dual one-shot or periodic 24bit timers,
the drivers set the first one as tick event source and the
second as a continuous scheduler clock source.
The timer can use 1, 16 or 256 as pre-dividers, thus the
clocksource uses 16
On Wed, Jun 15, 2016 at 11:48 AM, Jose Abreu wrote:
>
> On 15-06-2016 09:52, Daniel Vetter wrote:
>> On Tue, Jun 14, 2016 at 1:19 PM, Jose Abreu wrote:
I assume that xilinx VDMA is the only way to feed pixel data into your
display pipeline. Under that assumption:
drm_plane sho
ARM systems may be configured to have cpus with different power/performance
characteristics within the same chip. In this case, additional information
has to be made available to the kernel (the scheduler in particular) for it
to be aware of such differences and take decisions accordingly.
Therefo
Add Juno cpu capacity-dmips-mhz bindings information.
Cc: Rob Herring
Cc: Pawel Moll
Cc: Mark Rutland
Cc: Ian Campbell
Cc: Kumar Gala
Cc: Catalin Marinas
Cc: Will Deacon
Cc: Liviu Dudau
Cc: Sudeep Holla
Cc: Arnd Bergmann
Cc: Jon Medhurst
Cc: Olof Johansson
Cc: Robin Murphy
Cc: devicet
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