Introduce a new DOMAIN_ATTR_MSI_MAPPING domain attribute. If supported,
this means the MSI addresses need to be mapped in the IOMMU.
x86 IOMMUs typically don't expose the attribute since on x86, MSI write
transaction addresses always are within the 1MB PA region [FEE0_h -
FEF0_000h] window whi
This patch introduces iommu_get/put_reserved_iova.
iommu_get_reserved_iova allows to iommu map a contiguous physical region
onto a reserved contiguous IOVA region. The physical region base address
does not need to be iommu page size aligned. iova pages are allocated and
mapped so that they cover a
When the domain gets destroyed, let's make sure all reserved iova
resources get released.
Choice is made to put that call in arm-smmu(-v3).c to do something similar
to what was done for iommu_put_dma_cookie.
Signed-off-by: Eric Auger
---
v7: new
---
drivers/iommu/arm-smmu-v3.c | 2 ++
drivers
we will need to track which host physical addresses are mapped to
reserved IOVA. In that prospect we introduce a new RB tree indexed
by physical address. This RB tree only is used for reserved IOVA
bindings.
It is expected this RB tree will contain very few bindings. Those
generally correspond to
This patch introduces some new fields in the iommu_domain struct,
dedicated to reserved iova management.
In a similar way as DMA mapping IOVA window, we need to store
information related to a reserved IOVA window.
The reserved_iova_cookie will store the reserved iova_domain
handle. An RB tree ind
Introduce iommu_msi_mapping_translate_msg whose role consists in
detecting whether the device's MSIs must to be mapped into an IOMMU.
It case it must, the function overrides the MSI msg originally composed
and replaces the doorbell's PA by a pre-allocated and pre-mapped reserved
IOVA. In case the c
This series introduces the dma-reserved-iommu api used to:
- create/destroy an iova domain dedicated to reserved iova bindings
- map/unmap physical addresses onto reserved IOVAs.
- search for an existing reserved iova mapping matching a PA window
- determine whether an msi needs to be iommu mapped
On April 19, 2016 4:35:01 AM PDT, Borislav Petkov wrote:
>On Tue, Apr 19, 2016 at 01:15:30PM +0200, Ingo Molnar wrote:
>> So I'd suggest the following renames to harmonize these concepts:
>>
>> - CONFIG_IA32_EMULATION => CONFIG_X86_32_ABI
>>this lines up nicely with: CONFIG_X86_X32_ABI
>
>
- On Apr 19, 2016, at 10:34 AM, rostedt rost...@goodmis.org wrote:
> From: Steven Rostedt
>
> Add the infrastructure needed to have the PIDs in set_event_pid to
> automatically add PIDs of the children of the tasks that have their PIDs in
> set_event_pid. This will also remove PIDs from set
Majority of the callers of of_find_node_by_name() do not expect that it
will drop reference to the 'from' node if it was passed in, causing
potential refcount underflows, etc, so let's stop doing this.
Most of the callers that were handling dropping of reference done by
of_find_node_by_name() actu
Introduce alloc/free_reserved_iova_domain in the IOMMU API.
alloc_reserved_iova_domain initializes an iova domain at a given
iova base address and with a given size. This iova domain will
be used to allocate iova within that window. Those IOVAs will be reserved
for special purpose, typically MSI fr
On Tue, Apr 19, 2016 at 09:43:08AM +0200, H. Nikolaus Schaller wrote:
>
> > Am 18.04.2016 um 23:22 schrieb Dmitry Torokhov :
> >
> > On Mon, Apr 18, 2016 at 09:55:37PM +0200, H. Nikolaus Schaller wrote:
> >> commit e7ec014a47e4 ("Input: twl6040-vibra - update for device tree
> >> support")
> >>
On Tue, Apr 19, 2016 at 06:36:22AM -0400, Stefan Berger wrote:
> On 04/19/2016 06:12 AM, Jarkko Sakkinen wrote:
> >On Mon, Apr 18, 2016 at 01:26:13PM -0400, Stefan Berger wrote:
> >>From: Jason Gunthorpe
> >>
> >>The final thing preventing this was the way the sysfs files were
> >>attached to the
On Mon, Apr 18, 2016 at 05:55:51AM +, Reizer, Eyal wrote:
> > I would suggest fixing this using a new API function from the SPI core, if
> > we
> > don't already have a generic way to do it.
> Originally this is what I have done until I was pointed to the generic
> cs-gpio mechanism
> in t
Andrea, we provide the, ahem, adjustments to
transparent_hugepage_adjust. Rest assured we aggressively use mmu
notifiers with no further changes required.
As in: zero changes have been required in the lifetime (years) of
kvm+huge tmpfs at Google, other than mod'ing
transparent_hugepage_adjust.
As
On Tue, Apr 19, 2016 at 12:54:18PM +0300, Jarkko Sakkinen wrote:
> Cc: sta...@vger.kernel.org
> Fixes: 1bd047be37d9 ("tpm_crb: Use devm_ioremap_resource")
> Signed-off-by: Jarkko Sakkinen
> drivers/char/tpm/tpm_crb.c | 39 ---
> 1 file changed, 28 insertions(+)
On Tue, Apr 19, 2016 at 09:05:45AM +, Reizer, Eyal wrote:
> Understood. As this special CS manipulation is unique to wspi (wilink spi) I
> think the
> best option is to move this gpio allocation into wlcore_spi as a new device
> tree entry
> used only by this driver.
That sounds like it i
This patch handles the iommu mapping of MSI doorbells that require to
be mapped in an iommu domain. This happens on msi_domain_alloc/free_irqs
since this is called in code that can sleep (pci_enable/disable_msi):
iommu_map/unmap is not stated as atomic. On msi_domain_(de)activate and
msi_domain_set
On Tue, 19 Apr 2016 18:44:41 +0300
Grygorii Strashko wrote:
> On 04/19/2016 06:01 PM, David Rivshin (Allworx) wrote:
> > On Tue, 19 Apr 2016 17:41:07 +0300
> > Grygorii Strashko wrote:
> >
> >> Hi,
> >>
> >> On 04/19/2016 04:56 PM, Andrew Goodbody wrote:
> >>> Adding a 2nd PHY to cpsw resul
On Tue, 19 Apr 2016 16:55:11 + (UTC)
Mathieu Desnoyers wrote:
> - On Apr 19, 2016, at 10:34 AM, rostedt rost...@goodmis.org wrote:
>
> > From: Steven Rostedt
> >
> > Add the infrastructure needed to have the PIDs in set_event_pid to
> > automatically add PIDs of the children of the tas
This patch implements the msi_doorbell_info callback in the
gicv2m driver.
The driver now is able to return its doorbell characteristics
(base, size, prot). A single doorbell is exposed.
This will allow the msi layer to iommu_map this doorbell when
requested.
Signed-off-by: Eric Auger
---
v7:
On MSI message composition we now use the MSI doorbell's IOVA in
place of the doorbell's PA in case the device is upstream to an
IOMMU that requires MSI addresses to be mapped. The doorbell's
allocation and mapping happened on an early stage (pci_enable_msi).
Signed-off-by: Eric Auger
---
v6 ->
Currently the MSI message is composed by directly calling
irq_chip_compose_msi_msg and erased by setting the memory to zero.
On some platforms, we will need to complexify this composition to
properly handle MSI emission through IOMMU. Also we will need to track
when the MSI message is erased.
We
The purpose is to be able to retrieve the MSI doorbells of an irqchip.
This is now needed since on some platforms those doorbells must be
iommu mapped (in case the MSIs transit through an IOMMU that do not
bypass those transactions).
The assumption is there is a maximum of one doorbell region per
Add code to recognize SPARC-Sonoma cpu correctly and update cpu hardware
caps and cpu distribution map. SPARC-Sonoma is based upon SPARC-M7 core
along with additional PCI functions added on and is reported by firmware
as "SPARC-SN".
Signed-off-by: Khalid Aziz
---
arch/sparc/include/asm/spitfire.
On Tue, Apr 19, 2016 at 04:20:38PM +0100, Sudeep Holla wrote:
>
>
> On 19/04/16 16:05, Lorenzo Pieralisi wrote:
> >Hi Jisheng,
> >
> >On Tue, Mar 22, 2016 at 10:35:29PM +0800, Jisheng Zhang wrote:
> >>psci_dt_cpu_init_idle() and psci_cpu_init_idle() are not needed after
> >>booting, so mark them
Let's introduce a new msi_domain_info flag value, MSI_FLAG_IRQ_REMAPPING
meant to tell the domain supports IRQ REMAPPING, also known as Interrupt
Translation Service. On Intel HW this IRQ remapping capability is
abstracted on IOMMU side while on ARM it is abstracted on MSI controller
side. This fla
The ITS is the first ARM MSI controller advertising the new
MSI_FLAG_IRQ_REMAPPING flag. It does so because it supports
interrupt translation service. This HW support offers isolation
of MSIs, feature used when using KVM device passthrough.
Signed-off-by: Eric Auger
---
v5: new
---
drivers/irq
We plan to use msi_get_domain_info in VFIO module so let's export it.
Signed-off-by: Eric Auger
---
v2 -> v3:
- remove static implementation in case CONFIG_PCI_MSI_IRQ_DOMAIN is not set
---
kernel/irq/msi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/kernel/irq/msi.c b/kernel/irq/msi.c
This series implements the MSI address mapping/unmapping in the MSI layer.
IOMMU binding happens on pci_enable_msi since this function can sleep and
return errors. On msi_domain_set_affinity, msi_domain_(de)activate, which
are not allowed to sleep, we simply look for the already existing binding.
On Tue, 19 Apr 2016 16:55:28 + (UTC)
Mathieu Desnoyers wrote:
> - On Apr 19, 2016, at 10:34 AM, rostedt rost...@goodmis.org wrote:
>
> > From: Steven Rostedt
> >
> > In order to add the ability to let tasks that are filtered by the events
> > have their children also be traced on fork
On Tue, Apr 19, 2016 at 06:36:22AM -0400, Stefan Berger wrote:
> On 04/19/2016 06:12 AM, Jarkko Sakkinen wrote:
> >On Mon, Apr 18, 2016 at 01:26:13PM -0400, Stefan Berger wrote:
> >>From: Jason Gunthorpe
> >>
> >>The final thing preventing this was the way the sysfs files were
> >>attached to the
On 19/04/2016 16:59, Daniel Lezcano wrote:
> On Tue, Apr 19, 2016 at 04:05:19PM +0200, Mason wrote:
>> On 19/04/2016 15:13, Daniel Lezcano wrote:
>>
>>> On Tue, Apr 19, 2016 at 02:15:15PM +0200, Mason wrote:
>>>
From: Marc Gonzalez
Commit 0881841f7e78 changed "if (ret != 0)" to "if
Hi David,
> Am 19.04.2016 um 03:25 schrieb David Rivshin (Allworx)
> :
>
> Hi Nikolaus,
>
> I recently submitted a driver for the IS31FL32xx family of devices, so
> this driver caught my eye. I have a few comments below.
>
> On Mon, 18 Apr 2016 20:43:16 +0200
> "H. Nikolaus Schaller" wrote:
Hi Jacek,
> Am 19.04.2016 um 11:14 schrieb Jacek Anaszewski :
>
> Hi Nikolaus,
>
> Thanks for the patch. Please refer to my remarks in the code.
Thanks for the remarks!
>
> On 04/18/2016 08:43 PM, H. Nikolaus Schaller wrote:
>> This is a driver for the Integrated Silicon Solution Inc. LED dri
This patch allows the user-space to know whether MSI addresses need to
be mapped in the IOMMU. The user-space uses VFIO_IOMMU_GET_INFO ioctl and
IOMMU_INFO_REQUIRE_MSI_MAP gets set if they need to.
The computation of the number of IOVA pages to be provided by the user
space will be implemented in
The user is allowed to [un]register a reserved IOVA range by using the
DMA MAP API and setting the new flag: VFIO_DMA_MAP_FLAG_MSI_RESERVED_IOVA.
It provides the base address and the size. This region is stored in the
vfio_dma rb tree. At that point the iova range is not mapped to any target
addres
We introduce a vfio_dma type since we will need to discriminate
different types of dma slots:
- VFIO_IOVA_USER: IOVA region used to map user vaddr
- VFIO_IOVA_RESERVED: IOVA region reserved to map host device PA such
as MSI doorbells
Signed-off-by: Eric Auger
---
v6 -> v7:
- add VFIO_IOVA_ANY
On Tue, Apr 19, 2016 at 05:21:01PM +, Reizer, Eyal wrote:
> The main quirk here is that i need to send extra clocks after the spi init
> command while the CS pin is "high" in order to put the wilink chip into SPI
> mode.
> So just sending an empty transfer wouldnt do the trick here.
A singl
On Tue, 2016-04-19 at 19:20 +0300, Michael S. Tsirkin wrote:
>
> > I thought that PLATFORM served that purpose. Woudn't the host
> > advertise PLATFORM support and, if the guest doesn't ack it, the host
> > device would skip translation? Or is that problematic for vfio?
>
> Exactly that's probl
On Tue, Apr 19, 2016 at 07:21:20PM +0200, Mason wrote:
> On 19/04/2016 16:59, Daniel Lezcano wrote:
> > On Tue, Apr 19, 2016 at 04:05:19PM +0200, Mason wrote:
> >> On 19/04/2016 15:13, Daniel Lezcano wrote:
> >>
> >>> On Tue, Apr 19, 2016 at 02:15:15PM +0200, Mason wrote:
> >>>
> From: Marc Go
Hi Daniel,
On Fri, Mar 25, 2016 at 12:26:27PM +0100, Daniel Lezcano wrote:
> On 03/22/2016 03:42 PM, Jisheng Zhang wrote:
> >These trivial patches are similar as Masahiro posted in[1]. The main
> >purpose is let cpuidle_ops structure be constified and replace
> >"__initdata" with "__initconst".
>
In our RB-tree we now have slots of different types (USER and RESERVED).
It becomes useful to be able to search for dma slots of a specific type or
any type. This patch proposes an implementation for that modality and also
changes the existing callers using the USER type.
Signed-off-by: Eric Auger
Before allowing the end-user to create VFIO_IOVA_RESERVED dma slots,
let's implement the expected behavior for removal and replay. As opposed
to user dma slots, the physical pages bound to reserved IOVA do not need
to be pinned/unpinned. Also we currently handle a single reserved iova
domain. Any a
Do not advertise IOMMU_CAP_INTR_REMAP for arm-smmu(-v3). Indeed the
irq_remapping capability is abstracted on irqchip side for ARM as
opposed to Intel IOMMU featuring IRQ remapping HW.
So to check IRQ remapping capability, the msi domain needs to be
checked instead.
This commit needs to be applie
On x86 IRQ remapping is abstracted by the IOMMU. On ARM this is abstracted
by the msi controller. vfio_safe_irq_domain allows to check whether
interrupts are "safe" for a given device. They are if the device does
not use MSI or if the device uses MSI and the msi-parent controller
supports IRQ remap
This series allows the user-space to register a reserved IOVA domain.
This completes the kernel integration of the whole functionality on top
of part 1 & 2.
We reuse the VFIO DMA MAP ioctl with a new flag to bridge to the
dma-reserved-iommu API. The number of IOVA pages to provision for MSI
bindin
On Tue, Apr 19, 2016 at 06:31:14PM +0100, Lorenzo Pieralisi wrote:
> Hi Daniel,
>
> On Fri, Mar 25, 2016 at 12:26:27PM +0100, Daniel Lezcano wrote:
> > On 03/22/2016 03:42 PM, Jisheng Zhang wrote:
> > >These trivial patches are similar as Masahiro posted in[1]. The main
> > >purpose is let cpuidle
On Tue, Apr 19, 2016 at 05:50:23PM +0300, Erez Shitrit wrote:
> On Fri, Apr 15, 2016 at 1:17 PM, Hans Westgaard Ry
> wrote:
> > IPoIB collects statistics of traffic including number of packets
> > sent/received, number of bytes transferred, and certain errors. This
> > patch makes these statistics
On Mon, Apr 18, 2016 at 11:24:11AM -0700, Christoph Hellwig wrote:
> On Mon, Apr 18, 2016 at 11:40:47AM -0600, Jason Gunthorpe wrote:
> > I wasn't arguing this should integrate into verbs in some way, only
> > that the way to access the driver-specific uAPI of a RDMA device should
> > be through th
On 19/04/16 10:14, David Rivshin (Allworx) wrote:
>> Ah Ok. There are no user of cpsw_platform_data outside of net/ethernet/ti/,
>> so yes, looks like your patch 1 does exactly what's needed.
>
> Given that the v1 of Andrew's patch is already in Dave's net tree, and
> would obviously have many co
Hi Andrey,
When I enable KASAN for 4.5 and 4.6 (I didn't try with older versions),
I got FRAME_WARN warning for frame size exceeds 2048 bytes.
Then I found the kconfig looks like:
range 0 8192
default 0 if KASAN
default 1024 if !64BIT
default 2048 if 64BIT
In my understanding, FRAME_WARN sho
On Tue, Apr 19, 2016 at 12:26:44PM -0400, David Woodhouse wrote:
> On Tue, 2016-04-19 at 19:20 +0300, Michael S. Tsirkin wrote:
> >
> > > I thought that PLATFORM served that purpose. Woudn't the host
> > > advertise PLATFORM support and, if the guest doesn't ack it, the host
> > > device would sk
On Sat, 2016-04-09 at 21:51 +0100, Al Viro wrote:
> ... and use ITER_BVEC for the page part of request to send
>
> Signed-off-by: Al Viro
> ---
> fs/cifs/cifsproto.h | 2 -
> fs/cifs/transport.c | 141 +++---
> --
> 2 files changed, 41 insertions(+),
Use clk_prepare_enable and clk_disable_unprepare helpers. This also
fixes a sequence issue in the enable path which lead to a warning
on resume.
Signed-off-by: Stefan Agner
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 11 ++-
1 file changed, 2 insertions(+), 9 deletions(-)
diff --git
Implement a suspend/resume helper for CMA users which calls
drm_fb_helper_set_suspend.
Suggested-by: Thierry Reding
Signed-off-by: Stefan Agner
---
drivers/gpu/drm/drm_fb_cma_helper.c | 15 +++
include/drm/drm_fb_cma_helper.h | 1 +
2 files changed, 16 insertions(+)
diff --git
Use the drm_atomic_helper_suspend() and drm_atomic_helper_resume()
helpers to implement subsystem-level suspend/resume. This replaces
the (non-functional) regmap cache based suspend resume functionality.
Signed-off-by: Stefan Agner
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 39 +
Disable vblank events when CRTC gets disabled. This avoids an
external abort when entering suspend while disable_timer is still
active: On resume the timer might fire immediately and cause a
register access in fsl_dcu_drm_disable_vblank before clocks get
enabled by the resume function.
Signed-off-
Move the initialization code for layers into a separate function
in the plane file. This allows to reuse the function on resume.
Also move it at the very beginning which may not matter but makes
logically much more sense.
Signed-off-by: Stefan Agner
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
On 04/19/16 09:56, Paul E. McKenney wrote:
> On Tue, Apr 19, 2016 at 09:20:24AM -0700, Randy Dunlap wrote:
>> On 04/18/16 22:13, Stephen Rothwell wrote:
>>> Hi all,
>>>
>>> Changes since 20160418:
>>>
>>
>> on x86_64:
>>
>> kernel/built-in.o: In function `wake_torture_stats_print':
>> waketorture.c
On Sat, 2016-04-09 at 21:52 +0100, Al Viro wrote:
> Signed-off-by: Al Viro
> ---
> fs/cifs/cifsglob.h | 2 --
> fs/cifs/connect.c | 72
> --
> 2 files changed, 5 insertions(+), 69 deletions(-)
>
> diff --git a/fs/cifs/cifsglob.h b/fs/cifs/ci
This implements suspend/resume using the atomic update supsend/resume
helpers instead of the current implementation which uses regcache. The
code has been tested on a Colibri VF61 using the freeze suspend mode.
This also avoids a lockdep warning by not using register caching at
all and therefor ob
The tps6524x driver uses spi_dev_get() to take a copy of the SPI device
it uses but has no obvious reason to do so and never calls spi_dev_put()
to release the reference. Fix this to just a straight copy.
Signed-off-by: Mark Brown
---
drivers/regulator/tps6524x-regulator.c | 2 +-
1 file change
On Tue, Apr 19, 2016 at 05:38:02PM +, Reizer, Eyal wrote:
> Hi Mark,
>
> Hope you can see the attached picture that illustrates what need to sent for
> sucesfull SPI init.
I think what the picture shows is that you just need to send at least
one byte at the end of the transfer *after* deasse
Store the number of registers per layer in soc_data. This is
more consistent with how the rest of SoC specific data are
handled.
Signed-off-by: Stefan Agner
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c | 8 ++--
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 2 ++
drivers/gpu/drm/fsl-dcu/fsl
On Tue, Apr 19, 2016 at 10:49 AM, Michael S. Tsirkin wrote:
> On Tue, Apr 19, 2016 at 12:26:44PM -0400, David Woodhouse wrote:
>> On Tue, 2016-04-19 at 19:20 +0300, Michael S. Tsirkin wrote:
>> >
>> > > I thought that PLATFORM served that purpose. Woudn't the host
>> > > advertise PLATFORM suppor
Hi,
[auto build test ERROR on tip/irq/core]
[also build test ERROR on v4.6-rc4 next-20160419]
[if your patch is applied to the wrong git tree, please drop us a note to help
improving the system]
url:
https://github.com/0day-ci/linux/commits/Eric-Auger/KVM-PCIe-MSI-passthrough-on-ARM-ARM64
The cpsw_ndo_open() could try to access CPSW registers before
calling pm_runtime_get_sync(). This will trigger L3 error:
WARNING: CPU: 0 PID: 21 at drivers/bus/omap_l3_noc.c:147
l3_interrupt_handler+0x220/0x34c()
4400.ocp:L3 Custom Error: MASTER M2 (64-bit) TARGET L4_FAST (Idle): Data
Acce
Julia Lawall writes:
> Remove .owner field if calls are used which set it automatically
>
> Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci
Acked-by: Eric Anholt
signature.asc
Description: PGP signature
What I think we need is something like the patch below. In the long
ru nwe should also kill the mlx4_buf structure which now is pretty
pointless.
---
>From a493881d2a6c90152d3daabb7b6b3afd1d254d78 Mon Sep 17 00:00:00 2001
From: Christoph Hellwig
Date: Tue, 19 Apr 2016 14:12:14 -0400
Subject: mlx
On 19/04/2016 19:31, Daniel Lezcano wrote:
> On Tue, Apr 19, 2016 at 07:21:20PM +0200, Mason wrote:
>> On 19/04/2016 16:59, Daniel Lezcano wrote:
>>> On Tue, Apr 19, 2016 at 04:05:19PM +0200, Mason wrote:
On 19/04/2016 15:13, Daniel Lezcano wrote:
> On Tue, Apr 19, 2016 at 02:15:15PM
On Mon, Apr 18, 2016 at 10:26:10PM +0200, Jan Kara wrote:
> On Fri 15-04-16 22:05:31, Andrew Morton wrote:
> > On Thu, 14 Apr 2016 10:48:29 -0600 Toshi Kani wrote:
> >
> > > When CONFIG_FS_DAX_PMD is set, DAX supports mmap() using pmd page
> > > size. This feature relies on both mmap virtual add
On Sat, 2016-04-09 at 21:53 +0100, Al Viro wrote:
> just do ITER_BVEC recvmsg
>
> Signed-off-by: Al Viro
> ---
> fs/cifs/cifsproto.h | 7 +++---
> fs/cifs/connect.c | 65
> -
> fs/cifs/file.c | 53 ++
Kalle Valo writes:
> Jes Sorensen writes:
>
>> Arnd Bergmann writes:
>>> The references to some arrays in the rtl8xxxu driver were moved inside
>>> of an #ifdef, but the symbols remain outside, resulting in build warnings:
>>>
>>> rtl8xxxu/rtl8xxxu.c:1506:33: error:
>>> 'rtl8188ru_radioa_1t_high
Define a binding for the INA3221 Triple Current/Voltage Monitor.
Signed-off-by: Andrew F. Davis
---
Documentation/devicetree/bindings/hwmon/ina3221.txt | 19 +++
1 file changed, 19 insertions(+)
create mode 100644 Documentation/devicetree/bindings/hwmon/ina3221.txt
diff --git a
Hello all,
This series adds support for the INA3221 Triple Current/Voltage Monitor.
Changes from v1:
- rearranged and renumbered sysfs enteries
- added reading alert bits to sysfs
- removed internal power calculation
- added DT setting of shunt resistors
- various other minor fixups
Thanks,
Add support for the the INA3221 26v capable, Triple channel,
Bi-Directional, Zero-Drift, Low-/High-Side, Current/Voltage Monitor
with I2C interface.
Signed-off-by: Andrew F. Davis
---
Documentation/hwmon/ina3221 | 35
drivers/hwmon/Kconfig | 11 ++
drivers/hwmon/Makefile | 1
Make adjustments to the Intel 10G VF driver to support
running on Hyper-V hosts.
K. Y. Srinivasan (2):
ethernet: intel: Add the device ID's presented while running on
Hyper-V
intel: ixgbevf: Support Windows hosts (Hyper-V)
drivers/net/ethernet/intel/ixgbevf/defines.h |5 +
drive
On Hyper-V, the VF/PF communication is a via software mediated path
as opposed to the hardware mailbox. Make the necessary
adjustments to support Hyper-V.
Signed-off-by: K. Y. Srinivasan
---
V2: Addressed most of the comments from
Alexander Duyck
and Rustad, Mark
Linus Torvalds writes:
> On Fri, Apr 15, 2016 at 8:35 AM, Eric W. Biederman
> wrote:
>> The devpts filesystem has a notion of a system or primary instance of
>> devpts. To retain the notion of a primary system instance of devpts
>> the code needs a way to allow userspace to mount the internally
Intel SR-IOV cards present different ID when running on Hyper-V.
Add the device IDs presented while running on Hyper-V.
Signed-off-by: K. Y. Srinivasan
---
V4: No change from V1
drivers/net/ethernet/intel/ixgbevf/defines.h |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
On 4/19/2016 2:22 PM, Christoph Hellwig wrote:
> What I think we need is something like the patch below. In the long
> ru nwe should also kill the mlx4_buf structure which now is pretty
> pointless.
Maybe; this could be the correct approach if we can guarantee that the
architecture can allocate
On Mon, Apr 18, 2016 at 11:45:49PM -0400, Ira Weiny wrote:
> I'm a bit confused by what you are suggesting that "people will have to patch
> the driver with some vendor version if they really need it."?
>
> Could you elaborate?
There are lots of drivers where we simply did not accept these vendor
There is a build problem on ia64 that slipped by. It is easy to
correct, so I will have to send another version of the patches.
Sorry for the noise,
David Daney
On 04/18/2016 02:13 PM, David Daney wrote:
From: David Daney
Based on v16 of device-tree NUMA patch set for arm64 [1],this patch
> Add generic odd parity functions, adapted from
> "https://graphics.stanford.edu/~seander/bithacks.html#ParityParallel";
Given a PARITY_MAGIC of 0x6996, this is even parity, not odd.
(Which it should be; an XOR of all bits is the "natural" form.)
On 04/19/2016 08:14 PM, David Rivshin (Allworx) wrote:
On Tue, 19 Apr 2016 18:44:41 +0300
Grygorii Strashko wrote:
On 04/19/2016 06:01 PM, David Rivshin (Allworx) wrote:
On Tue, 19 Apr 2016 17:41:07 +0300
Grygorii Strashko wrote:
Hi,
On 04/19/2016 04:56 PM, Andrew Goodbody wrote:
Adding
On Tue, Apr 19, 2016 at 06:04:49PM +, Reizer, Eyal wrote:
> Thanks! Glad the illustration helped.
> I will try it out again as if i recall cotrectly, i did try that l, and it
> didnt produce the correct waveform, but perhaps i didnt understand the usage
> of .cs_change correctly.
> Will doub
On Tue, Apr 19, 2016 at 11:09:53AM -0600, Jason Gunthorpe wrote:
> On Tue, Apr 19, 2016 at 12:54:18PM +0300, Jarkko Sakkinen wrote:
> > Cc: sta...@vger.kernel.org
> > Fixes: 1bd047be37d9 ("tpm_crb: Use devm_ioremap_resource")
> > Signed-off-by: Jarkko Sakkinen
> > drivers/char/tpm/tpm_crb.c | 39
Hi Tomi,
Just a humble suggestion/nitpick.
On 18 April 2016 at 16:46, Tomi Valkeinen wrote:
> Add Tomi Valkeinen as omapdrm maintainer.
>
> Signed-off-by: Tomi Valkeinen
> Cc: Rob Clark
> Cc: Laurent Pinchart
> ---
> MAINTAINERS | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a
On April 19, 2016 11:22:24 AM PDT, ebied...@xmission.com wrote:
>Linus Torvalds writes:
>
>> On Fri, Apr 15, 2016 at 8:35 AM, Eric W. Biederman
>> wrote:
>>> The devpts filesystem has a notion of a system or primary instance
>of
>>> devpts. To retain the notion of a primary system instance of de
On Tue, Mar 22, 2016 at 10:42:42PM +0800, Jisheng Zhang wrote:
> The qcom_cpuidle_ops structures is not over-written, so add "const"
> qualifier and replace __initdata with __initconst.
>
> Signed-off-by: Jisheng Zhang
Acked-by: Andy Gross
Linus Torvalds writes:
> What this does is get rid of the horrible notion of having that
>
> struct inode *ptmx_inode
>
> be the interface between the pty code and devpts. By de-emphasizing the
> ptmx inode, a lot of things actually get cleaner, and we will have a much
> saner way forward.
Ok, I see your point, but it seems that minimum address that a process is
allowed to map is mmap_min_addr and not dac_mmap_min_addr.
This is because mmap_min_addr can be seen as the max(dac_mmap_min_addr,
CONFIG_LSM_MMAP_MIN_ADDR) which is correct (the minimum allowed address) but
/proc/sys/vm/mmap
Jann Horn writes:
> On Fri, Apr 15, 2016 at 10:35:20AM -0500, Eric W. Biederman wrote:
>> +static inline bool is_dev_ptmx(struct inode *inode)
>> +{
>> +return inode->i_rdev == MKDEV(TTYAUX_MAJOR, PTMX_MINOR);
>> +}
>
> I'm not sure whether it matters, but I think a FUSE filesystem
> should b
On April 19, 2016 10:19:47 AM PDT, Steven Rostedt wrote:
>On Tue, 19 Apr 2016 16:55:28 + (UTC)
>Mathieu Desnoyers wrote:
>
>> - On Apr 19, 2016, at 10:34 AM, rostedt rost...@goodmis.org
>wrote:
>>
>> > From: Steven Rostedt
>> >
>> > In order to add the ability to let tasks that are fil
On April 19, 2016 11:22:24 AM PDT, ebied...@xmission.com wrote:
>Linus Torvalds writes:
>
>> On Fri, Apr 15, 2016 at 8:35 AM, Eric W. Biederman
>> wrote:
>>> The devpts filesystem has a notion of a system or primary instance
>of
>>> devpts. To retain the notion of a primary system instance of de
nel.org/pub/scm/linux/kernel/git/acme/linux into perf/core
> (2016-04-16 11:09:57 +0200)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git
> tags/perf-core-for-mingo-20160419
>
> for you to fetch changes up to 6566
On 19/04/16 08:22, Laxman Dewangan wrote:
> In some of platform, thermal sensors like NCT thermistors are
> connected to the one of ADC channel. The temperature is read by
> reading the voltage across the sensor resistance via ADC. Lookup
> table for ADC read value to temperature is referred to get
Hi Hoan,
On Tue, Apr 5, 2016 at 11:14 PM, hotran wrote:
> ACPI 6.1 has a HW-Reduced Communication Subspace Type 2 intended for
> use on HW-Reduce ACPI Platform, which requires read-modify-write sequence
> to acknowledge doorbell interrupt. This patch provides the implementation
> for the Communic
On 04/12/2016 02:33 AM, Srinivas Kandagatla wrote:
> This patch adds pmic regulator supplies connected on the board.
> Rest of the invidual regulators would be added as and when required by
> the devices.
>
> Signed-off-by: Srinivas Kandagatla
> Acked-by: Bjorn Andersson
> ---
> arch/arm/boot/dt
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