Hi Balbi and Mina,
On 30/03/16 13:33, Michal Nazarewicz wrote:
> On Wed, Mar 30 2016, Felipe Balbi wrote:
>> a USB packet, right. that's correct. But a struct usb_request can
>> point to whatever size buffer it wants and UDC is required to split
>> that into wMaxPacketSize transfers.
>
> D’oh. O
On 04/01/2016 10:08 AM, Crt Mori wrote:
> On 31 March 2016 at 19:20, Crestez Dan Leonard
> wrote:
>> Using this requires software triggers like CONFIG_IIO_HRTIMER_TRIGGER.
> Then we are missing DEPENDS in Kconfig...
The device could be used with any generic trigger. The device driver
shouldn't ma
On 01/04/16 11:15, Peter Zijlstra wrote:
> On Fri, Apr 01, 2016 at 11:03:21AM +0200, Juergen Gross wrote:
>>> Maybe just make the vpin thing an option like:
>>>
>>> smp_call_on_cpu(int (*func)(void *), int phys_cpu);
>
>>> Also; is something like the vpin thing possible on KVM? because if we'r
my comment was about your comment that MSR have wrapped however many times
> On Apr 1, 2016, at 10:03 AM, Peter Zijlstra wrote:
>
> That is; if userspace doesn't request a freq reading we can go without
> reading this for a very long time.
>
>> +
>> +rdmsrl(MSR_IA32_APERF, aperf);
>> +
Hi Paul,
On 03/21/16 19:44, Paul Walmsley wrote:
> Hi Péter,
>
> On Mon, 21 Mar 2016, Peter Ujfalusi wrote:
>
>> On 03/19/16 21:38, Paul Walmsley wrote:
>>> On Fri, 18 Mar 2016, Peter Ujfalusi wrote:
>>>
Hi,
Chanes since v1:
- removed the ASoC patch as Mark has applied it alr
On Tue, 29 Mar 2016, Gabriele Mazzotta wrote:
> input_mt_get_slot_by_key() requires input_mt_sync_frame() to be called
> at each frame. Do it when releasing the touches, or else we won't get
> a proper slot number after mt_reset_resume().
>
> Signed-off-by: Gabriele Mazzotta
Queued for 4.6. Tha
Hello Petr,
On (04/01/16 10:59), Petr Mladek wrote:
[..]
> CPU0 CPU1
>
> printk()
>
> if (printk_kthread)
> # fails and need_flush_console
> # stays false
>
> init_printk_kthread()
>
On Fri, Apr 01, 2016 at 11:30:48AM +0200, Stephane Gasparini wrote:
> my comment was about your comment that MSR have wrapped however many times
>
Yes, and don't top post.
On Wed, 2 Mar 2016, Heiner Kallweit wrote:
> Based on the proposed RGB LED core extension the thingm driver was
> changed to make use of this extension. It allows to simplify
> the code a lot. For now primary purpose of this patch is to facilitate
> testing of the RGB LED core extension.
>
> I di
Hi Pali,
[auto build test WARNING on v4.6-rc1]
[cannot apply to pcmoore-selinux/next next-20160401]
[if your patch is applied to the wrong git tree, please drop us a note to help
improving the system]
url:
https://github.com/0day-ci/linux/commits/Pali-Roh-r/Security-Rename-SELinux-to
2016-03-31 19:55 GMT+02:00 Srinivas Pandruvada
:
> On Thu, 2016-03-31 at 19:27 +0200, Jörg Otte wrote:
>> 2016-03-31 17:43 GMT+02:00 Rafael J. Wysocki :
>> > On Thursday, March 31, 2016 05:25:18 PM Jörg Otte wrote:
>> > > 2016-03-31 13:42 GMT+02:00 Rafael J. Wysocki :
>> > > > On Thursday, March 31
On 04/01/2016 10:58 AM, Felipe Balbi wrote:
>
> Hi,
>
> Grygorii Strashko writes:
>> On 03/31/2016 11:04 AM, Felipe Balbi wrote:
>>> "Thang Q. Nguyen" writes:
[ text/plain ]
Thanks Grygorii for information.
I checked but do not see dma_init_dev_from_parent is used in
linux-n
From: David Daney
Define a new symbol (ARCH_SUPPORTS_LIBUNWIND) in config/Makefile.
Use this from x86 and MIPS to gate testing of libunwind.
Signed-off-by: David Daney
Cc: linux-m...@linux-mips.org
Cc: Jiri Olsa
Cc: linux-kernel@vger.kernel.org
Cc: Peter Zijlstra
Cc: Paul Mackerras
Cc: Ingo
On Fri, Apr 01, 2016 at 11:30:48AM +0200, Stephane Gasparini wrote:
> The MSRs will not wrap that often.
Unless some yahoo goes and does WRMSR APERF .
I think we should handle that gracefully too, regardless of how "smart"
that move might be.
--
Regards/Gruss,
Boris.
ECO tip #101: Trim you
A long time ago David Daney submitted patches to add MIPS support to
perf-tools. Running out of out of time the the series the minor reviewer
comments were never dealt with so I now picked up the series and am posting
a version 3.
David Daney (3):
MIPS: Add user stack and registers to perf.
p
* Michal Hocko wrote:
> On Fri 01-04-16 08:33:48, Ingo Molnar wrote:
> [...]
> > I can help on the Git level: I can do tip:locking/rwsem tree with only
> > these
> > changes, with stable sha1's, on which the remaining work can be based. The
> > locking tree typically goes in early during the m
From: David Daney
This allows for extracting off-line stack traces from user-space code
in the perf tool.
[r...@linux-mips.org: Add perf_get_regs_user() which is required after
88a7c26af8da (perf: >> Move task_pt_regs sampling into arch code).]
Signed-off-by: David Daney
Cc: linux-m...@linux-m
From: David Daney
Hack up the Makefile and add support code for mips unwinding
and dwarf-regs.
Signed-off-by: David Daney
Cc: linux-m...@linux-mips.org
Cc: Jiri Olsa
Cc: linux-kernel@vger.kernel.org
Cc: Peter Zijlstra
Cc: Paul Mackerras
Cc: Ingo Molnar
Cc: Arnaldo Carvalho de Melo
Signed-o
On 04/01/2016 12:15 AM, Nishanth Menon wrote:
Palams extcon IRQs are nested threaded and wired to the Palmas
inerrupt controller. So, this flag is not required for nested
irqs anymore, since commit 3c646f2c6aa9 ("genirq: Don't suspend
nested_thread irqs over system suspend") was merged. However,
On Fri, 2016-04-01 at 17:06 +0800, Kefeng Wang wrote:
> Commit cdcea058e510("serial: 8250_dw: Avoid serial_outx code
> duplicate
> with new dw8250_check_lcr()") introduce a wrong logic when write val
> to
> LCR reg. When CONFIG_64BIT enabled, __raw_writeq is used
> unconditionally.
>
> But for !PO
Implement extended BPF JIT for ppc64. We retain the classic BPF JIT for
ppc32 and move ppc64 BE/LE to use the new JIT. Classic BPF filters will
be converted to extended BPF (see convert_filter()) and JIT'ed with the
new compiler.
Most of the existing macros are retained and fixed/enhanced where
ap
The existing LI32() macro can sometimes result in a sign-extended 32-bit
load that does not clear the top 32-bits properly. As an example,
loading 0x7fff results in the register containing
0x7fff. While this does not impact classic BPF JIT
implementation (since that only uses the lo
Break out classic BPF JIT specifics into a separate header in
preparation for eBPF JIT implementation. Note that ppc32 will still need
the classic BPF JIT.
Cc: Matt Evans
Cc: Michael Ellerman
Cc: Paul Mackerras
Cc: Alexei Starovoitov
Cc: "David S. Miller"
Cc: Ananth N Mavinakayanahalli
Signe
PPC64 eBPF JIT compiler. Works for both ABIv1 and ABIv2.
Enable with:
echo 1 > /proc/sys/net/core/bpf_jit_enable
or
echo 2 > /proc/sys/net/core/bpf_jit_enable
... to see the generated JIT code. This can further be processed with
tools/net/bpf_jit_disasm.
With CONFIG_TEST_BPF=m and 'modprobe test
1. Per the ISA, ADDIS actually uses RT, rather than RS. Though
the result is the same, make the usage clear.
2. The multiply instruction used is a 32-bit multiply. Rename PPC_MUL()
to PPC_MULW() to make the same clear.
3. PPC_STW[U] take the entire 16-bit immediate value and do not require
word-ali
On Fri, Apr 1, 2016 at 7:55 AM, Zheng, Lv wrote:
> Hi,
Hi Lv,
>> Add support for acpi_user_table configfs items that allows the user to
>> load new tables. The data attributes contains the table data and once it
>> is filled from userspace the table is loaded and ACPI devices are
>> enumerated.
Similar to the LI32() optimization, if the value can be represented
in 32-bits, use LI32(). Also handle loading a few specific forms of
immediate values in an optimum manner.
While at it, remove the semicolon at the end of the macro!
Cc: Matt Evans
Cc: Michael Ellerman
Cc: Paul Mackerras
Cc: A
Since we will be using the rotate immediate instructions for extended
BPF JIT, let's introduce macros for the same. And since the shift
immediate operations use the rotate immediate instructions, let's redo
those macros to use the newly introduced instructions.
Cc: Matt Evans
Cc: Michael Ellerman
On Fri, Apr 1, 2016 at 8:05 AM, Zheng, Lv wrote:
> Hi,
>
> IMO, there is already a similar function upstreamed:
> https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=c85cc81
> Could it work for your use case?
Yes, it is basically the same.
The only difference is on how we
This patch adds related DTS binding document for HiSilicon RoCE driver.
Signed-off-by: Lijun Ou
Signed-off-by: Wei Hu(Xavier)
---
.../bindings/infiniband/hisilicon-hns-roce.txt | 107 +
1 file changed, 107 insertions(+)
create mode 100644
Documentation/devicetree/bindi
On 03/31/2016 11:58 PM, Richard Weinberger wrote:
During page migrations UBIFS gets confused. We triggered this by using CMA
on two different targets.
It turned out that fallback_migrate_page() is not suitable for UBIFS as it
does not copy the PagePrivate flag.
UBIFS is using this flag among with
It added reset function for RoCE driver. RoCE is a feature of hns.
In hip06 SoC, in RoCE reset process, it's needed to configure dsaf
channel reset, port and sl map info. Reset function of RoCE is
located in dsaf module, we only call it in RoCE driver when needed.
Signed-off-by: Lijun Ou
Signed-o
The HiSilicon Network Substem is a long term evolution IP which is
supposed to be used in HiSilicon ICT SoC. RoCE is a feature of hns.
The driver for HiSilicon RoCE engine is a platform driver.
The driver will support mulitple versions of hns. Currently only "v1"
for hip06 SoC is supported.
Change
On 03/31/2016 11:58 PM, Richard Weinberger wrote:
From: "Kirill A. Shutemov"
During page migrations UBIFS might get confused
and the following assert triggers:
UBIFS assert failed in ubifs_set_page_dirty at 1451 (pid 436)
It would be useful to have the full trace in changelog.
UBIFS is usin
On Thu, Mar 24, 2016 at 05:53:40PM +, Julien Grall wrote:
> Fill up the recently introduced gic_kvm_info with the hardware
> information used for virtualization.
>
> Signed-off-by: Julien Grall
> Cc: Thomas Gleixner
> Cc: Jason Cooper
> Cc: Marc Zyngier
>
> ---
> Changes in v4:
>
Hi,
Grygorii Strashko writes:
>> if of_dma_configure() does what you want, why don't you just stick it in
>> dwc3-keystone.c and let the driver continue to copy things for now ?
>> Something like below, perhaps ?
>>
>
> I know (and i have patch to fix that which I'm going to send) that DMA conf
Cc'ing Rob and Mason.
On 30-03-16, 09:53, Arnd Bergmann wrote:
> I think it should be something in the /cpus or the /opp_table hierarchy,
> not the root of the device tree, but other than that I don't care much
> whether it's a variation of the oppv2 compatible string or an additional
> property i
Hi,
Felipe Ferreri Tonello writes:
> Hi Balbi and Mina,
>
> On 30/03/16 13:33, Michal Nazarewicz wrote:
>> On Wed, Mar 30 2016, Felipe Balbi wrote:
>>> a USB packet, right. that's correct. But a struct usb_request can
>>> point to whatever size buffer it wants and UDC is required to split
>>> th
On 2016/3/31 20:42, Mark Rutland wrote:
> On Thu, Mar 31, 2016 at 01:44:08PM +0200, Ard Biesheuvel wrote:
>> > The heuristic is there to decide whether some DTB image contains a
>> > complete description of the platform, or only some data handed over by
>> > the bootloader. Arguably, a DT contain
On 01/04/16 11:13, Christoffer Dall wrote:
> On Thu, Mar 24, 2016 at 05:53:40PM +, Julien Grall wrote:
>> Fill up the recently introduced gic_kvm_info with the hardware
>> information used for virtualization.
>>
>> Signed-off-by: Julien Grall
>> Cc: Thomas Gleixner
>> Cc: Jason Cooper
>> Cc:
On 2016/04/01 03:28PM, Naveen N Rao wrote:
> Implement extended BPF JIT for ppc64. We retain the classic BPF JIT for
> ppc32 and move ppc64 BE/LE to use the new JIT. Classic BPF filters will
> be converted to extended BPF (see convert_filter()) and JIT'ed with the
> new compiler.
>
> Most of the e
Hi, Arnaldo
Thank you for your review.
On 04/01/2016 02:31 AM, Arnaldo Carvalho de Melo wrote:
Em Tue, Mar 29, 2016 at 09:43:13AM +0900, Taeung Song escreveu:
This infrastructure code was designed for
upcoming features of perf-config.
That collect config key-value pairs from user and
system c
On Thu, Mar 31, 2016 at 06:12:38PM -0400, Waiman Long wrote:
> On 03/29/2016 04:20 PM, Peter Zijlstra wrote:
> >>cnts = atomic_add_return_acquire(_QR_BIAS,&lock->cnts) - _QR_BIAS;
> >>+ while ((cnts& _QW_WMASK) == _QW_LOCKED) {
> >>+ if (locked&& ((cnts>> _QR_SHIFT)< MAX_SPINNIN
On Thu, Mar 31, 2016 at 06:12:38PM -0400, Waiman Long wrote:
> >>However, if we allow a limited number of readers to spin on the
> >>lock simultaneously, we can eliminates some of the reader-to-reader
> >>latencies at the expense of a bit more cacheline contention and
> >>probably more power consum
On Thu, Mar 24, 2016 at 05:53:42PM +, Julien Grall wrote:
> Currently, the firmware tables are parsed 2 times: once in the GIC
> drivers, the other time when initializing the vGIC. It means code
> duplication and make more tedious to add the support for another
> firmware table (like ACPI).
>
On 2016/4/1 17:25, Shannon Zhao wrote:
> If it really needs is_xen_node(), I will not factor
> fdt_find_hyper_node() in patch 11 since it uses flat DT while here it's
> going to use unflatten DT.
Sorry, I'm wrong. They both use flat DT. But it's no need to factor
fdt_find_hyper_node() since is_xe
* Thomas Gleixner | 2016-03-14 09:49:52 [+0100]:
>On Sun, 13 Mar 2016, Clark Williams wrote:
>
>> I'm hitting the WARN_ON(wakes > 2) in $SUBJECT when resuming from suspend on
>> my laptop (quad-core i7 with HT on). Looks like the warning gets hit 36
>> times on resume. E.g.:
>If resume is the on
Hi Linus,
Please pull powerpc fixes for 4.6:
The following changes since commit f55532a0c0b8bb6148f4e07853b876ef73bc69ca:
Linux 4.6-rc1 (2016-03-26 16:03:24 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git
tags/powerpc-4.6-2
f
Hello.
On 4/1/2016 1:21 AM, Bin Liu wrote:
Simplify things a bit by using devm functions where possible.
Signed-off-by: David Lechner
---
v3 changes:
* Kept clk variable to minimize noise.
drivers/usb/musb/da8xx.c | 19 +--
1 file changed, 5 insertions(+), 14 deletions(
On 31.03.2016 11:04, Mika Westerberg wrote:
> On Wed, Mar 30, 2016 at 06:05:30PM +0300, Cristina Ciocan wrote:
>> +PINCTRL_PIN(55, "GPIO_S0_SC[055]"),
>> +PINCTRL_PIN(56, "GPIO_S0_SC[056]"),
>> +PINCTRL_PIN(57, "GPIO_S0_SC[057]"),
>> +PINCTRL_PIN(58, "GPIO_S0_SC[058]"),
>> +PINC
On Fri, Apr 01, 2016 at 12:31:43PM +0200, Peter Zijlstra wrote:
> On Thu, Mar 31, 2016 at 06:12:38PM -0400, Waiman Long wrote:
> > >>However, if we allow a limited number of readers to spin on the
> > >>lock simultaneously, we can eliminates some of the reader-to-reader
> > >>latencies at the expen
This patch fixes condition whether the specified address ranges
overlap each other.
Fixes: 4b7f48d395a7 ("bus: uniphier-system-bus: add UniPhier System Bus driver")
Signed-off-by: Kunihiko Hayashi
---
drivers/bus/uniphier-system-bus.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff -
On 01.04.2016 06:55, Rajesh Bhagat wrote:
Please share your opinion on other changes for patch submission as well as
resume
time.
I think more effort should be put into investigating why this happens in the
first place.
What is the root cause? why doesn't xhci start properly after resu
On Wednesday 16 March 2016 15:47:10 Sebastian Reichel wrote:
> I just had another look at the driver and I think there is a race
> condition for tpa6130a2_add_controls() and tpa6130a2_stereo_enable().
>
> As far as I can see both functions check for "tpa6130a2_client !=
> NULL". tpa6130a2_client i
Hi,
[TL;DR; This patch set needs more review, if you're using OP-TEE please
help reviewing.]
This patch set introduces a generic TEE subsystem. The TEE subsystem will
contain drivers for various TEE implementations. A TEE (Trusted Execution
Environment) is a trusted OS running in some secure envi
Acked-by: Andreas Dannenberg
Signed-off-by: Jens Wiklander
---
Documentation/00-INDEX | 2 +
Documentation/tee.txt | 118 +
MAINTAINERS| 1 +
3 files changed, 121 insertions(+)
create mode 100644 Documentation/tee.txt
diff --git
Initial patch for generic TEE subsystem.
This subsystem provides:
* Registration/un-registration of TEE drivers.
* Shared memory between normal world and secure world.
* Ioctl interface for interaction with user space.
* Sysfs implementation_id of TEE driver
A TEE (Trusted Execution Environment) d
Adds a OP-TEE driver which also can be compiled as a loadable module.
* Targets ARM and ARM64
* Supports using reserved memory from OP-TEE as shared memory
* Probes OP-TEE version using SMCs
* Accepts requests on privileged and unprivileged device
* Uses OPTEE message protocol version 2 to communi
Introduces linaro prefix and adds bindings for ARM TrustZone based OP-TEE
implementation.
Acked-by: Rob Herring
Signed-off-by: Jens Wiklander
---
.../bindings/arm/firmware/linaro,optee-tz.txt | 31 ++
.../devicetree/bindings/vendor-prefixes.txt| 1 +
2 files ch
On Fri 01-04-16 11:50:00, Ingo Molnar wrote:
>
> * Michal Hocko wrote:
>
> > On Fri 01-04-16 08:33:48, Ingo Molnar wrote:
> > [...]
> > > I can help on the Git level: I can do tip:locking/rwsem tree with only
> > > these
> > > changes, with stable sha1's, on which the remaining work can be bas
This patch updates the gpio chip implementation in order to interact with
the pin control model: the chip contains reference to SOC data and
pin/group/community information is retrieved through the SOC reference.
Signed-off-by: Cristina Ciocan
---
drivers/pinctrl/intel/pinctrl-baytrail.c | 97 ++
This patch updates the irq chip implementation in order to interact with
the pin control chip model: the chip contains reference to SOC data and
pin/group/community information is retrieved through the SOC reference.
Signed-off-by: Cristina Ciocan
---
drivers/pinctrl/intel/pinctrl-baytrail.c | 9
Add implementation for:
- pin control, group information retrieval: count, name and pins
- pin muxing:
- function information (count, name and groups)
- mux setting
- gpio control (enable, disable, set direction)
- pin configur
In order to implement pin control for Baytrail, we need data structures
in which to store and pass along pin, group, function, community and SOC
data information.
Baytrail has 3 GPIO controllers. Add SCORE, NCORE and SUS controller data:
- pins (for all controllers),
- pad map for
This patch updates device's probing, removal and irq handling in order to
register it as pinctrl device. Pin control data is matched by ACPI UID,
since it is passed along as driver data in acpi_device_id structure.
Signed-off-by: Cristina Ciocan
---
drivers/pinctrl/intel/pinctrl-baytrail.c | 447
Make debounce setting and getting functionality available when
configurating a certain pin.
Signed-off-by: Cristina Ciocan
---
drivers/pinctrl/intel/pinctrl-baytrail.c | 83 +++-
1 file changed, 81 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/intel/pinc
This patch updates device's probing, removal and irq handling in order to
register it as pinctrl device. Pin control data is matched by ACPI UID,
since it is passed along as driver data in acpi_device_id structure.
Signed-off-by: Cristina Ciocan
---
drivers/pinctrl/intel/pinctrl-baytrail.c | 447
This patch updates the gpio chip implementation in order to interact with
the pin control model: the chip contains reference to SOC data and
pin/group/community information is retrieved through the SOC reference.
Signed-off-by: Cristina Ciocan
---
drivers/pinctrl/intel/pinctrl-baytrail.c | 97 ++
On Thu, Mar 31, 2016 at 8:29 PM, Mark Brown wrote:
> On Thu, Mar 31, 2016 at 12:37:02PM +0300, Octavian Purdila wrote:
>
>> +#if IS_ENABLED(CONFIG_ACPI)
>> +static int acpi_spi_table_load(struct device *dev, const void *data)
>> +{
>> + struct spi_master *master = container_of(dev, struct spi_
Make debounce setting and getting functionality available when
configurating a certain pin.
Signed-off-by: Cristina Ciocan
---
drivers/pinctrl/intel/pinctrl-baytrail.c | 83 +++-
1 file changed, 81 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/intel/pinc
On Fri, Apr 01, 2016 at 11:41:19AM +0100, Will Deacon wrote:
> On Fri, Apr 01, 2016 at 12:31:43PM +0200, Peter Zijlstra wrote:
> > On Thu, Mar 31, 2016 at 06:12:38PM -0400, Waiman Long wrote:
> > > >>However, if we allow a limited number of readers to spin on the
> > > >>lock simultaneously, we can
Add implementation for:
- pin control, group information retrieval: count, name and pins
- pin muxing:
- function information (count, name and groups)
- mux setting
- gpio control (enable, disable, set direction)
- pin configur
This patch updates the irq chip implementation in order to interact with
the pin control chip model: the chip contains reference to SOC data and
pin/group/community information is retrieved through the SOC reference.
Signed-off-by: Cristina Ciocan
---
drivers/pinctrl/intel/pinctrl-baytrail.c | 9
Add support for pin control (pin muxing and pin configuration) for Baytrail
platform.
It follows the design in pinctrl-intel.c, but could not use the
implementation in pinctrl-intel since there were significant differences:
- gpio pin pads are not ordered
- per group functions: for
This patch updates device's probing, removal and irq handling in order to
register it as pinctrl device. Pin control data is matched by ACPI UID,
since it is passed along as driver data in acpi_device_id structure.
Signed-off-by: Cristina Ciocan
---
drivers/pinctrl/intel/pinctrl-baytrail.c | 447
In order to implement pin control for Baytrail, we need data structures
in which to store and pass along pin, group, function, community and SOC
data information.
Baytrail has 3 GPIO controllers. Add SCORE, NCORE and SUS controller data:
- pins (for all controllers),
- pad map for
Add support for pin control (pin muxing and pin configuration) for Baytrail
platform.
It follows the design in pinctrl-intel.c, but could not use the
implementation in pinctrl-intel since there were significant differences:
- gpio pin pads are not ordered
- per group functions: for
On 01.04.2016 13:56, Cristina Ciocan wrote:
> Add support for pin control (pin muxing and pin configuration) for Baytrail
> platform.
>
> It follows the design in pinctrl-intel.c, but could not use the
> implementation in pinctrl-intel since there were significant differences:
> - gpio pin p
Hello.
On 4/1/2016 11:56 AM, Ralf Baechle wrote:
From: David Daney
Define a new symbol (ARCH_SUPPORTS_LIBUNWIND) in config/Makefile.
Eh? Where is it?
Use this from x86 and MIPS to gate testing of libunwind.
x86? Where?
Signed-off-by: David Daney
Cc: linux-m...@linux-mips.org
Cc
This patch updates the gpio chip implementation in order to interact with
the pin control model: the chip contains reference to SOC data and
pin/group/community information is retrieved through the SOC reference.
Signed-off-by: Cristina Ciocan
---
drivers/pinctrl/intel/pinctrl-baytrail.c | 97 ++
Add implementation for:
- pin control, group information retrieval: count, name and pins
- pin muxing:
- function information (count, name and groups)
- mux setting
- gpio control (enable, disable, set direction)
- pin configur
Make debounce setting and getting functionality available when
configurating a certain pin.
Signed-off-by: Cristina Ciocan
---
drivers/pinctrl/intel/pinctrl-baytrail.c | 83 +++-
1 file changed, 81 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/intel/pinc
In order to implement pin control for Baytrail, we need data structures
in which to store and pass along pin, group, function, community and SOC
data information.
Baytrail has 3 GPIO controllers. Add SCORE, NCORE and SUS controller data:
- pins (for all controllers),
- pad map for
This patch updates the irq chip implementation in order to interact with
the pin control chip model: the chip contains reference to SOC data and
pin/group/community information is retrieved through the SOC reference.
Signed-off-by: Cristina Ciocan
---
drivers/pinctrl/intel/pinctrl-baytrail.c | 9
I found a kernel crash while playing with deadline PI rtmutex.
BUG: unable to handle kernel NULL pointer dereference at 0018
IP: [] rt_mutex_get_top_task+0x1f/0x30
PGD 232a75067 PUD 230947067 PMD 0
Oops: [#1] SMP
CPU: 1 PID: 10994 Comm: a.out Not tainted
C
On 04/01/2016 01:20 PM, Felipe Balbi wrote:
>
> Hi,
>
> Grygorii Strashko writes:
>>> if of_dma_configure() does what you want, why don't you just stick it in
>>> dwc3-keystone.c and let the driver continue to copy things for now ?
>>> Something like below, perhaps ?
>>>
>>
>> I know (and i have
Most ->get() functions seem to call BUG_ON() if offset + len is out of
range, but rproc_virtio_get() returns early without initializing ret.
Presumably it can't actually happen but it leads to a static checker
warning. Let's just initialize "ret".
Signed-off-by: Dan Carpenter
diff --git a/inclu
The static checker checker is warning that we could hit the first
continue; on every iteration through the loop and never initialize
"ret". It seems unlikely but we may as well silence the warning.
Signed-off-by: Dan Carpenter
diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c
b/drivers/gpu/dr
From: Michal Hocko
Introduce ___down_write for the fast path and reuse it for __down_write
resp. __down_write_killable each using the respective generic slow path
(rwsem_down_write_failed resp. rwsem_down_write_failed_killable).
Signed-off-by: Michal Hocko
---
arch/ia64/include/asm/rwsem.h | 2
My static checker complains that "ret" could be uninitialized at the
end, which is true but it's more likely that it would be set to zero.
Signed-off-by: Dan Carpenter
diff --git a/drivers/uio/uio.c b/drivers/uio/uio.c
index bcc1fc0..fba021f 100644
--- a/drivers/uio/uio.c
+++ b/drivers/uio/uio.c
From: Michal Hocko
Now that all the architectures implement the necessary glue code
we can introduce down_write_killable. The only difference wrt. regular
down_write is that the slow path waits in TASK_KILLABLE state and the
interruption by the fatal signal is reported as -EINTR to the caller.
S
From: Michal Hocko
sh and xtensa seem to be the only architectures which use explicit
memory barriers for rw_semaphore operations even though they are not
really needed because there is the full memory barrier is always implied
by atomic_{inc,dec,add,sub}_return resp. cmpxchg. Remove them.
Signe
From: Michal Hocko
This is no longer used anywhere and all callers (__down_write) use
0 as a subclass. Ditch __down_write_nested to make the code easier
to follow.
This shouldn't introduce any functional change.
Signed-off-by: Michal Hocko
---
arch/s390/include/asm/rwsem.h | 7 +--
arch
Hi,
the following patchset implements a killable variant of write lock
for rw_semaphore. My usecase is to turn as many mmap_sem write users
to use a killable variant which will be helpful for the oom_reaper
merged in 4.6-rc1 (aac453635549 ("mm, oom: introduce oom reaper")) to
asynchronously tear do
From: Michal Hocko
which uses the same fast path as __down_write except it falls back to
rwsem_down_write_failed_killable slow path and return -EINTR if killed.
Signed-off-by: Michal Hocko
---
arch/sparc/include/asm/rwsem.h | 13 +
1 file changed, 13 insertions(+)
diff --git a/arc
From: Michal Hocko
which uses the same fast path as __down_write except it falls back to
rwsem_down_write_failed_killable slow path and return -EINTR if killed.
Signed-off-by: Michal Hocko
---
arch/sh/include/asm/rwsem.h | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/s
From: Michal Hocko
which uses the same fast path as __down_write except it falls back to
call_rwsem_down_write_failed_killable slow path and return -EINTR if
killed. To prevent from code duplication extract the skeleton of
__down_write into a helper macro which just takes the semaphore
and the sl
From: Michal Hocko
Introduce ___down_write for the fast path and reuse it for __down_write
resp. __down_write_killable each using the respective generic slow path
(rwsem_down_write_failed resp. rwsem_down_write_failed_killable).
Signed-off-by: Michal Hocko
---
arch/s390/include/asm/rwsem.h | 1
From: Michal Hocko
which uses the same fast path as __down_write except it falls back to
rwsem_down_write_failed_killable slow path and return -EINTR if killed.
Signed-off-by: Michal Hocko
---
arch/xtensa/include/asm/rwsem.h | 13 +
1 file changed, 13 insertions(+)
diff --git a/ar
From: Michal Hocko
Introduce a generic implementation necessary for down_write_killable.
This is a trivial extension of the already existing down_write call
which can be interrupted by SIGKILL. This patch doesn't provide
down_write_killable yet because arches have to provide the necessary
pieces
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