On Tue, Feb 09, 2016 at 06:37:46PM -0800, Guenter Roeck wrote:
> On 02/09/2016 07:26 AM, Arnd Bergmann wrote:
> >On Tuesday 09 February 2016 07:08:59 Guenter Roeck wrote:
> >>IS_ERR_VALUE() assumes that its parameter is an unsigned long.
> >>It can not be used to check if an unsigned int reflects a
On Thu, Feb 11, 2016 at 10:10:00AM +0100, Arnd Bergmann wrote:
> After the drm_device_is_unplugged() was removed, the 'dev' variable is now
> unused, and we get a warning for that:
>
> drivers/gpu/drm/msm/msm_fbdev.c: In function 'msm_fbdev_mmap':
> drivers/gpu/drm/msm/msm_fbdev.c:65:21: error: un
The Spansion s25fl116k is a 16MBit NOR Flash supporting dual and
quad read operations.
Signed-off-by: Sascha Hauer
---
changes since v1:
- actually make it compile
drivers/mtd/spi-nor/spi-nor.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-
On Wed 10-02-16 23:39:43, Cedric Blancher wrote:
> AFAIK Solaris 11 uses a sparse tree instead of a array. Solves the
> scalability problem AND deals with variable page size.
Well, but then you have to have this locking tree for every inode so the
memory overhead is relatively large, no? I've play
On 27/01/16 02:24, Biao Huang wrote:
Add pinctrl and GPIO node to mt2701.dtsi
Signed-off-by: Biao Huang
Acked-by: Linus Walleij
---
Applied, thanks.
Hi Sascha,
[auto build test ERROR on v4.5-rc3]
[also build test ERROR on next-20160211]
[if your patch is applied to the wrong git tree, please drop us a note to help
improving the system]
url:
https://github.com/0day-ci/linux/commits/Sascha-Hauer/mtd-spi-nor-Add-support-for-s25fl116k
On 09/02/16 11:04, Robin Murphy wrote:
> The existing msi-map code is fine for shifting the entire RID space
> upwards, but attempting finer-grained remapping reveals a bug. It turns
> out that we are mistakenly treating the msi-base part as an offset, not
> as a new base to remap onto, so things g
On Thu, Feb 11, 2016 at 10:46:08AM +0100, Ulf Hansson wrote:
> [...]
>
> >> >
> >> >> Currently, sdhci disables card detect interrupts when runtime suspended,
> >> >> and drivers use a card-detect GPIO to wake-up.
> >> >>
> >> >
> >> > It is what I have seen going through the sdhci layer. So next
Stephen,
The upstream patch. Enjoy!
The following changes since commit 36f90b0a2ddd60823fe193a85e60ff1906c2a9b3:
Linux 4.5-rc2 (2016-01-31 18:12:16 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git tags/ib-mfd-clk-v4.6
for you to fet
On 02/11/2016 11:41 AM, Lars-Peter Clausen wrote:
> On 02/11/2016 10:08 AM, Peter Ujfalusi wrote:
>> We need the callback to support the dmaengine_terminate_sync().
>>
>> Signed-off-by: Peter Ujfalusi
>
> Looks good, but I noticed a slight race condition in
> edma_completion_handler(). You need t
On Wed 10-02-16 16:32:53, Ross Zwisler wrote:
> On Thu, Feb 11, 2016 at 09:09:53AM +1100, Dave Chinner wrote:
> > On Wed, Feb 10, 2016 at 11:32:49AM +0100, Jan Kara wrote:
> > > On Tue 09-02-16 10:18:53, Dan Williams wrote:
> > > > On Tue, Feb 9, 2016 at 9:24 AM, Jan Kara wrote:
> > > > > Hello,
>
Ville,
here is another dmesg: [1]
I've reconnected HDMI cable three times.
Forgot to note, it is HDMI monitor plugged into machine's DVI with
HDMI-DVI cable. I guess this should matter as well.
[1] https://gist.github.com/7057ea8512b9aa7ee5bd
11.02.2016 11:26, Ville Syrjälä написав:
On Thu
On Wed, Feb 10, 2016 at 10:21:21AM +0100, Daniel Wagner wrote:
> Depending on the configuration either the 32 or 64 bit version of
> elf_check_arch() is defined. parse_crash_elf{32|64}_headers() does
> some basic verification of the ELF header via
> vmcore_elf{32|64}_check_arch() which happen to m
s/FW_CTRL_DATA_OFF/FW_CFG_DATA_OFF/
Signed-off-by: Valentin Rothberg
Signed-off-by: Andreas Ziegler
---
v2: corrected typo in signed-off-by
drivers/firmware/qemu_fw_cfg.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/firmware/qemu_fw_cfg.c b/drivers/firmware/qemu_
On Thu, 11 Feb 2016 16:23:33 +0530
Vineet Gupta wrote:
> On Thursday 11 February 2016 03:52 PM, Martin Schwidefsky wrote:
> > On Thu, 11 Feb 2016 14:58:26 +0530
> > Vineet Gupta wrote:
> >
> >> Generic pgtable_trans_huge_deposit()/pgtable_trans_huge_withdraw()
> >> assume pgtable_t to be struct
s/FW_CTRL_DATA_OFF/FW_CFG_DATA_OFF/
Signed-off-by: Valentin Rothberg
Signed-off-by: Anreads Ziegler
---
drivers/firmware/qemu_fw_cfg.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/firmware/qemu_fw_cfg.c b/drivers/firmware/qemu_fw_cfg.c
index 19f6851be87f..fedbff55
On 07/02/16 11:42, John Crispin wrote:
This patch adds a new struct pwrap_slv_type that we use to store the slave
specific data. The patch adds 2 new helper functions to access the dew
registers. The slave type is looked up via the wrappers child node.
Signed-off-by: John Crispin
---
Changes
On Sat, Jan 30, 2016 at 6:06 PM, Nicolas Saenz Julienne
wrote:
> Driver for the GPIO block found in ti's tps65218 pmics.
>
> The device has two GPIOs and one GPO pin which can be configured as follows:
> GPIO1:
> -general-purpose, open-drain output controlled by GPO1 user bit and/or
>
Commit 7d34d56ef334 ("PM / OPP: Disable OPPs that aren't supported by
the regulator") disables OPPs that are not supported by the regulator.
This is causes a crash on Tegra124 Jetson TK1 when using the DFLL clock
source for the CPU. The DFLL manages the voltage itself and so there is
no regulator s
On Wed, Feb 10, 2016 at 01:26:22PM -0600, ttha...@opensource.altera.com wrote:
> From: Thor Thayer
>
> Adding the device tree entries and bindings needed to support
> the Altera L2 cache and On-Chip RAM EDAC. This patch relies upon
> an earlier patch to declare and setup On-chip RAM properly.
> h
On 07/02/16 11:42, John Crispin wrote:
Add support for MT6323 slaves. This PMIC can be found on MT2701 and MT7623
EVB. The only function that we need to touch is pwrap_init_cipher().
Signed-off-by: John Crispin
---
drivers/soc/mediatek/mtk-pmic-wrap.c | 47
On 11-02-16, 11:25, Jon Hunter wrote:
> Commit 7d34d56ef334 ("PM / OPP: Disable OPPs that aren't supported by
> the regulator") disables OPPs that are not supported by the regulator.
> This is causes a crash on Tegra124 Jetson TK1 when using the DFLL clock
> source for the CPU. The DFLL manages the
On 10/02/16 20:10, Kenneth Westfield wrote:
On Wed, Feb 10, 2016 at 02:20:03AM -0800, Srinivas Kandagatla wrote:
diff --git a/sound/soc/qcom/lpass-platform.c
b/sound/soc/qcom/lpass-platform.c
index 26a046a..574aa33 100644
--- a/sound/soc/qcom/lpass-platform.c
+++ b/sound/soc/qcom/lpass-platfor
On Wed, Feb 10, 2016 at 01:32:50PM -0500, Dick Kennedy wrote:
> Martin,
> the FCP_RING_POLLING feature is an old driver option that we would like to
> remove from the driver. It was put in in 2006 as a feature request.
> What we don't know is if any customers still use it? or ever used it.
>
> T
On Wed, Feb 10, 2016 at 01:26:21PM -0600, ttha...@opensource.altera.com wrote:
> From: Thor Thayer
>
> Adding L2 Cache and On-Chip RAM EDAC support for the
> Altera SoCs using the EDAC device model. The SDRAM
> controller is using the Memory Controller model.
>
> Each type of ECC is individuall
PPAs sent to device is separately acknowledge in a 64bit status
variable. The status is stored in DW0 and DW1 of the completion queue
entry. Store this status inside the nvm_rq for further processing.
This can later be used to implement retry techniques for failed writes
and reads.
Signed-off-by:
For LightNVM, the PPA completion status is communicated through DW0 and
DW1 of the completion queue entry. The patch is based on top of
Christoph's
"nvme: return the whole CQE through the request passthrough interface"
that exposes the full CQE during completion.
Matias Bjørling (1):
nvme: li
(+RobH and MarkR)
On 09.02.16 15:35:42, Ard Biesheuvel wrote:
> (+ Grant)
>
> On 9 February 2016 at 14:53, Robert Richter
> wrote:
> > From: Robert Richter
> >
> > Reposting an updated version of this patches ported to 4.5-rc1. It is
> > a followup to the version 3 from:
> >
> >
> > http://l
On 07/02/16 11:42, John Crispin wrote:
Add the registers, callbacks and data structures required to make the
wrapper work on MT2701 and MT7623.
Signed-off-by: John Crispin
---
drivers/soc/mediatek/mtk-pmic-wrap.c | 162 ++
1 file changed, 162 insertions(+)
Philipp Hahn wrote:
> Am 25.09.2015 um 17:54 schrieb David Howells:
> > Can you pass these changes on to Linus? There are four:
> ...
> > (3) Don't strip leading zeros from the key ID when using it to construct a
> > key description lest this make the key not match.
>
> That commit e7c87b
On 11-02-16, 02:15, Rafael J. Wysocki wrote:
> And one question tangentially related to this patch: Would it be
> possible to avoid calling __cpufreq_governor(_EXIT) for CPU offline?
>
> The fact that we still carry out the whole governor teardown at that
> point is slightly disturbing, as in theo
Hi John,
On 07/02/16 11:42, John Crispin wrote:
This series adds support for a new PMIC (MT6323) and 2 new SoCs
(MT2701/7623) to the pmic-wrap driver.
John Crispin (11):
dt-bindings: ARM: Mediatek: add MT2701/7623 string to the PMIC
wrapper doc
soc: mediatek: PMIC wrap: don't duplic
On Thu 2016-02-11 17:21:12, Sergey Senozhatsky wrote:
> Hello,
> Thanks for Cc-ing, and sorry for long reply, I'm traveling now.
>
> On (02/10/16 11:25), Steven Rostedt wrote:
> > On Wed, 10 Feb 2016 17:10:16 +0100
> > Petr Mladek wrote:
> >
> > > > Note, it's not that performance critical, and
Thomas, Hanjun,
On 19/01/16 13:11, Tomasz Nowicki wrote:
> Patches base on Suravee's ACPI GICv2m support:
> https://lkml.org/lkml/2015/12/10/475
>
> The following git branch contains submitted patches along with
> the useful patches from the test point of view (mainly ACPI ARM64 PCI
> support).
On Tue, Feb 09, 2016 at 09:05:05PM +0100, Rafael J. Wysocki wrote:
> > > One concern I had was, given that the lone scheduler update hook is in
> > > CFS, is it possible for governor updates to be stalled due to RT or DL
> > > task activity?
> >
> > I don't think they may be completely stalled, bu
On 11-02-16, 10:48, Rafael J. Wysocki wrote:
> On Tue, Feb 9, 2016 at 4:46 AM, Viresh Kumar wrote:
> > Also note that cpufreq_driver->stop_cpu() and ->exit() can get called
> > while policy->rwsem is held. That shouldn't have any side effects
> > though.
>
> The last paragraph is unclear.
>
> Is
On 07/02/16 11:42, John Crispin wrote:
This patch moves the SoC specific wrapper init code into separate callback
to avoid pwrap_init() getting too large.
Please explain a bit more, what the patch does.
Signed-off-by: John Crispin
---
Changes in V5
* only check the return code of init_spe
On Wed, Feb 10, 2016 at 11:27:50AM -0800, Luck, Tony wrote:
> Digging in the data sheet I found the CAPID0 register which does
> indicate in bit 4 whether this is an "EX" (a.k.a. "E7" part). But
> we invent a new PCI device ID for this every generation (0x0EC3 in
> Ivy Bridge, 0x2fc0 in Haswell, 0x
On Thu, Feb 04, 2016 at 06:29:00PM +0100, Tomasz Nowicki wrote:
> This is the last step before enabling generic ACPI PCI host controller
> for ARM64. We need to take care of legacy IRQ mapping for non-MSI(X)
> PCI devices. pcibios_enable_device() boot order is not sensitive to
> ACPI device enumera
On 07/02/16 11:42, John Crispin wrote:
MT2701 and MT7623 use a different bitmask for the SPI_WRITE command.
Something like:
Different SoCs will use different bitmask for the SPI_WRITE command.
This patch defines the bitmask in the pmic_wrapper_type to allow an easy
addition.
Well you are
On Sun, Jan 31, 2016 at 2:20 AM, Vishnu Patekar
wrote:
> The A83T has R_PIO pin controller, it's same as A23, execpt A83T
> interrupt bit is 6th and A83T has one extra pin PL12.
>
> Signed-off-by: Vishnu Patekar
Maxime, can you look at this patch?
Yours,
Linus Walleij
On 07/02/16 11:42, John Crispin wrote:
Make the handling of wdt_src consitent with the rest of the code.
Same here, please explain what the patch is doing. Or just squash 6 and
7, as you like.
On Tue, Feb 09, 2016 at 05:02:33PM -0800, Steve Muckle wrote:
> > Index: linux-pm/kernel/sched/deadline.c
> > ===
> > --- linux-pm.orig/kernel/sched/deadline.c
> > +++ linux-pm/kernel/sched/deadline.c
> > @@ -1197,6 +1197,9 @@ static v
On 07/02/16 11:42, John Crispin wrote:
With more SoCs being added the list of helper functions like these would
grow. While at it also add a new flag "has_bridge" and use that instead of
pwrap_is_mt8173() where appropriate.
Signed-off-by: John Crispin
---
Same here, please explain better wh
Hi Rafael,
These are rest of the patches that fix some more locking issues with
policy->rwsem and do some minor optimization/cleanups.
V4->V5:
- Changelog updated for 1-2 as suggested by Rafael
- 4th patch is dropped, which moved common tunable callbacks to
cpufreq_governor.c
- 5-7 are resend o
Governor sysfs attributes are still removed in
__cpufreq_governor(_EXIT), though, so had store() been used for them,
the deadlock described in the changelog of commit 1aee40ac9c86 would
have been possible.
Fortunately, we don't use store() (which still does get_online_cpus())
for those attributes
In __cpufreq_cooling_register() we allocate the arrays for time_in_idle
and time_in_idle_timestamp to be as big as the number of cpus in this
cpufreq device. However, in get_load() we access this array using the
cpu number as index, which can result in an out of bound access.
Index time_in_idle{,
The cpufreq core now guarantees that policy->rwsem won't be dropped
while running the ->governor callback for the CPUFREQ_GOV_POLICY_EXIT
event and will be held acquired until the complete sequence of governor
state changes has finished.
This allows governor state machine checks to be dropped from
Ondemand governor already updates sample_delay_ns immediately on updates
to sampling rate, but conservative isn't doing that.
It was left out earlier as the code has been really complex to get that
done easily. But now things are sorted out very well, and we can follow
the same for conservative go
'delay' is updated properly in all paths of the routine od_dbs_timer(),
leaving just one. And can be 0 only in that case.
Move the update to 'delay' as an else part of the if block.
Signed-off-by: Viresh Kumar
---
drivers/cpufreq/cpufreq_ondemand.c | 9 -
1 file changed, 4 insertions(+)
On 2016-02-03, Peter Hurley wrote:
The DMA-enabled OMAP UART driver in its current form queues 48
bytes for a DMA-RX transfer. After the transfer is complete, a new
transfer of 48 bytes is queued. The DMA completion callback runs in
tasklet context, so a reschedule with context
The cpufreq core code is not consistent with respect to invoking
__cpufreq_governor() under policy->rwsem.
Changing all code to always hold policy->rwsem around
__cpufreq_governor() invocations will allow us to remove
cpufreq_governor_lock, that is used today because we can't guarantee
that __cpuf
We used to drop policy->rwsem just before calling __cpufreq_governor()
in some cases earlier and so it was possible that __cpufreq_governor()
runs concurrently via separate threads.
In order to guarantee valid state transitions for governors,
'governor_enabled' was required to be protected using s
On Tue, Feb 2, 2016 at 11:03 AM, Krzysztof Adamski
wrote:
> It seems that on H3, just like on A10, when GPIOs are configured as
> external interrupt data registers does not contain their value. When
> value is read, GPIO function must be temporary switched to input for
> reads.
>
> Signed-off-by
On Thu, 11 Feb 2016, Ralf Baechle wrote:
> > Signed-off-by: Daniel Wagner
> > Suggested-by: Maciej W. Rozycki
> > Reviewed-by: Maciej W. Rozycki
> > Reported-by: Fengguang Wu
>
> Thanks, applied.
>
> I'm getting a less spectacular warning from gcc 5.2:
>
> CC fs/proc/vmcore.o
> fs/pr
On 08/02/16 14:36, Arnd Bergmann wrote:
The mtk8250_runtime_suspend function is not used when runtime PM is
disabled, so we get a warning about an unused function:
drivers/tty/serial/8250/8250_mtk.c:119:12: error: 'mtk8250_runtime_suspend'
defined but not used [-Werror=unused-function]
stat
Add SW support for MAXIM Semiconductor's Power Management
IC (PMIC) MAX77620/MAX20024. This PMIC supports DC-DC/LDOS, GPIOs,
RTC, watchdog, clocks etc.
This series add respective driver for each of sub-modules.
---
Changes from V1:
DT DOC:
- Added units in some of properties.
- Change the boolean
On Thu, Feb 11, 2016 at 12:51 PM, Peter Zijlstra wrote:
> On Tue, Feb 09, 2016 at 09:05:05PM +0100, Rafael J. Wysocki wrote:
>> > > One concern I had was, given that the lone scheduler update hook is in
>> > > CFS, is it possible for governor updates to be stalled due to RT or DL
>> > > task activ
The MAXIM PMIC MAX77620 and MAX20024 are power management IC
which supports RTC, GPIO, DCDC/LDO regulators, interrupt,
watchdog etc.
Add DT binding document for the different functionality of
this device.
Signed-off-by: Laxman Dewangan
Acked-by: Rob Herring
---
Changes from V1:
- Added units i
Maxim Semiconductor's PMIC MAX77620/MAX20024 has 8 GPIO pins
which act as GPIO as well as special function mode.
Add DT binding document to support these pins in GPIO
mode via GPIO framework.
Signed-off-by: Laxman Dewangan
Acked-by: Rob Herring
---
Changes from V4:
- Separate out from gpio dri
Maxim Semiconductor's PMIC MAX77620/MAX20024 has 8 GPIO pins
which act as GPIO as well as special function mode.
Add DT binding document to configure pins in function mode as
well as pin configuration parameters.
Signed-off-by: Laxman Dewangan
Acked-by: Rob Herring
---
Changes from V4:
- Separ
MAXIM Semiconductor's PMIC, MAX77620/MAX20024 has 8 GPIO pins
which also act as the special function in alternate mode. Also
there is configuration like push-pull, open drain, FPS timing
etc for these pins.
Add pincontrol driver to configure these parameters through
pincontrol APIs.
Signed-off-by
MAX77620/MAX20024 are Power Management IC from the MAXIM.
It supports RTC, multiple GPIOs, multiple DCDC and LDOs,
watchdog, clock etc.
Add MFD drier to provides common support for accessing the
device; additional drivers is developed on respected subsystem
in order to use the functionality of the
Maxim Semiconductor's PMIC MAX77620/MAX20024 has multiple
DCDCs and LDOs.
Add DT binding document to support these regulators via
regulator framework.
Signed-off-by: Laxman Dewangan
Acked-by: Rob Herring
---
Changes from V4:
- Separate out from regulator driver
Changes from V6:
- Starting pat
MAXIM Semiconductor's PMIC, MAX77620/MAX20024 has 8 GPIO
pins. It also supports interrupts from these pins.
Add GPIO driver for these pins to control via GPIO APIs.
Signed-off-by: Laxman Dewangan
Reviewed-by: Linus Walleij
---
Changes from V1:
- Use the gpiochip_add_data and get the chip data
MAXIM Semiconductor's PMIC, MAX77620 and MAX20024 have the
multiple DCDC and LDOs. This supplies the power to different
components of the system.
Also these rails has configuration for ramp time, flexible
power sequence, slew rate etc.
Add regulator driver to access these rails via regulator APIs.
On 10/02/16 16:27, Juri Lelli wrote:
> On 10/02/16 09:37, Steven Rostedt wrote:
> > On Wed, 10 Feb 2016 11:32:58 +
> > Juri Lelli wrote:
> >
[...]
> >
> > I applied this patch and patch 2 and hit this:
> >
[...]
> >
> > It's the warning you added in __dl_sub_ac().
> >
>
> OK. There a
On Thu, Feb 11, 2016 at 12:19:03PM +0100, Valentin Rothberg wrote:
> s/FW_CTRL_DATA_OFF/FW_CFG_DATA_OFF/
Thanks for catching that !
Acked-by: Gabriel Somlo
>
> Signed-off-by: Valentin Rothberg
> Signed-off-by: Andreas Ziegler
> ---
> v2: corrected typo in signed-off-by
>
> drivers/firmwar
Adding UFS 2.0 support to the UFS core driver.
Signed-off-by: Joao Pinto
---
Changes v0->v7:
- Nothing changed (just to keep up with patch set version).
drivers/scsi/ufs/ufshcd.c | 29 +
drivers/scsi/ufs/ufshci.h | 1 +
2 files changed, 26 insertions(+), 4 deletions
This patch has the goal to add support for DesignWare UFS Controller
specific operations and to add specific platform and pci drivers.
Signed-off-by: Joao Pinto
---
Changes v6->v7 (Arnd Bergmann):
- Changed DT node name (to ufs only) and the memory address (to 0xd00)
- Removed CONFIG_PM from
The work consisted of:
- Fixed typo in ufshcd-pltfrm.c
- Tweak ufshcd.c for UFS 2.0 support
- Implement ufshcd-dwc which contains all DWC HW specific code
- Unipro attributes were added and new registers were added to the driver
- Implement a ufs-dwc glue platform driver
- Implement a ufs-dwc-pci g
Fixed typo in ufshcd-pltfrm.
Signed-off-by: Joao Pinto
---
Changes v0->v7:
- Nothing changed (just to keep up with patch set version).
drivers/scsi/ufs/ufshcd-pltfrm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/scsi/ufs/ufshcd-pltfrm.c b/drivers/scsi/ufs/ufshcd-
On 02/11/2016 01:04 PM, Maciej W. Rozycki wrote:
> On Thu, 11 Feb 2016, Ralf Baechle wrote:
>> Thanks, applied.
>>
>> I'm getting a less spectacular warning from gcc 5.2:
>>
>> CC fs/proc/vmcore.o
>> fs/proc/vmcore.c: In function ‘parse_crash_elf64_headers’:
>> fs/proc/vmcore.c:939:47: warni
On 11 February 2016 at 12:42, Robert Richter
wrote:
> (+RobH and MarkR)
>
> On 09.02.16 15:35:42, Ard Biesheuvel wrote:
>> (+ Grant)
>>
>> On 9 February 2016 at 14:53, Robert Richter
>> wrote:
>> > From: Robert Richter
>> >
>> > Reposting an updated version of this patches ported to 4.5-rc1. It
LPASS IP on QCOM SOC supports both Playback and capture
via I2S, but this feature is missing in existing code.
This patchset aims at adding capture support to lpass IP.
First few patches in this series does cleanup the driver
to make easy to add capture support.
All these patches are acked by Ken
There is no point in having local allocation functions when the driver
can use snd_dma_alloc/free() apis. This patch replaces the local versions
of the dma allocation apis with the snd_dma_alloc/free() apis.
Signed-off-by: Srinivas Kandagatla
Acked-by: Kenneth Westfield
---
sound/soc/qcom/lpass
This patch updates the internal dma allocation callbacks to take the
stream direction so that it can allocate channels suitable for that
stream direction. Before the capture support this was not necessary.
Signed-off-by: Srinivas Kandagatla
Acked-by: Kenneth Westfield
---
sound/soc/qcom/lpass-a
rdma_ch_bit_map can be reused for wrdma channel allocations as wrdma
channel numbering start after rdma channel numbers.
With capture support referring rdma_ch_bit_map for wrdma channel allocation
is confusing, so renaming rdma_ch_bit_map to dma_ch_bit_map makes sense.
Signed-off-by: Srinivas Kand
This patch adds wrdma related register offsets, wrdma channel start
and shifts into lpass variant structure.
Signed-off-by: Srinivas Kandagatla
Acked-by: Kenneth Westfield
---
sound/soc/qcom/lpass.h | 4
1 file changed, 4 insertions(+)
diff --git a/sound/soc/qcom/lpass.h b/sound/soc/qcom/
This patch renames rdmactl_audif_start to dmactrl_audif_start as this
is common for both rdma and wrdma. Without this patch the name would be
bit misleading to the readers.
Signed-off-by: Srinivas Kandagatla
Acked-by: Kenneth Westfield
---
sound/soc/qcom/lpass-apq8016.c | 2 +-
sound/soc/qcom/
This patch adds mic related bitmasks and offsets in the i2c control
register.
Signed-off-by: Srinivas Kandagatla
Acked-by: Kenneth Westfield
---
sound/soc/qcom/lpass-lpaif-reg.h | 22 ++
1 file changed, 22 insertions(+)
diff --git a/sound/soc/qcom/lpass-lpaif-reg.h b/sound/
ipq806x is only ever tested for playback so return error in dma allocation
if the stream direction is capture.
Signed-off-by: Srinivas Kandagatla
Acked-by: Kenneth Westfield
---
sound/soc/qcom/lpass-ipq806x.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/sound/soc/qcom
This patch adds wrdma registers into the lpaif-reg.h.
Signed-off-by: Srinivas Kandagatla
Acked-by: Kenneth Westfield
---
sound/soc/qcom/lpass-lpaif-reg.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/sound/soc/qcom/lpass-lpaif-reg.h b/sound/soc/qcom/lpass-lpaif-reg.h
index 65
This patch adds mic support to the lpass driver, most of the driver is
reused as it is, only the register level access is changed depending on
te direction of the stream.
Signed-off-by: Srinivas Kandagatla
Acked-by: Kenneth Westfield
---
sound/soc/qcom/lpass-cpu.c | 113 +++
Now that we are ready to access wrdma registers, set the max register
and other regmap related configs to use correct values.
Signed-off-by: Srinivas Kandagatla
Acked-by: Kenneth Westfield
---
sound/soc/qcom/lpass-cpu.c | 33 +++--
1 file changed, 31 insertions(+), 2
This patch adds generic masks for accessing bits in rdma/wrdma
registers. Doing this would simplify the driver and adding capture
support would be much simpler. Also there is no point in having same
bit masks for bits in both rdma and wrdma registers.
This patch also deletes the RDMA specific bit
This patch add mic support on apq8016-sbc board aka db410c. Tested it
with headset mic.
Signed-off-by: Srinivas Kandagatla
Acked-by: Kenneth Westfield
---
sound/soc/qcom/apq8016_sbc.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/sound/soc/qcom/apq8016_sbc.c b/s
This patch adds wrdma support in lpass-apq8016 by providing the register
offsets and adding support in dma channel allocation callback.
Signed-off-by: Srinivas Kandagatla
Acked-by: Kenneth Westfield
---
sound/soc/qcom/lpass-apq8016.c | 22 +++---
1 file changed, 19 insertions(+)
From: Simon Xiao
Date: Thu, 4 Feb 2016 15:49:34 -0800
> 1. Adding NETIF_F_TSO6 feature flag;
> 2. Adding NETIF_F_HW_CSUM. NETIF_F_IPV6_CSUM and NETIF_F_IP_CSUM are
> being deprecated;
> 3. Cleanup the coding style of flag assignment by using macro.
>
> Signed-off-by: Simon Xiao
> Reviewed-by:
This patch adds wrdma related register offsets to the lpass variant data
of ipq806x.
Signed-off-by: Srinivas Kandagatla
Acked-by: Kenneth Westfield
---
sound/soc/qcom/lpass-ipq806x.c | 4
1 file changed, 4 insertions(+)
diff --git a/sound/soc/qcom/lpass-ipq806x.c b/sound/soc/qcom/lpass-ip
On 02/11/2016 05:04 AM, js1...@gmail.com wrote:
> From: Joonsoo Kim
>
> We can disable debug_pagealloc processing even if the code is compiled
> with CONFIG_DEBUG_PAGEALLOC. This patch changes the code to query
> whether it is enabled or not in runtime.
>
> v2: clean up code, per Christian.
>
>
Hi Juri,
On Thu, 11 Feb 2016 12:12:57 +
Juri Lelli wrote:
[...]
> I think we still have (at least) two problems:
>
> - select_task_rq_dl, if we select a different target
> - select_task_rq might make use of select_fallback_rq, if
> cpus_allowed changed after the task went to sleep
>
> Sec
Hi Peter,
On 11/02/16 12:59, Peter Zijlstra wrote:
> On Tue, Feb 09, 2016 at 05:02:33PM -0800, Steve Muckle wrote:
> > > Index: linux-pm/kernel/sched/deadline.c
> > > ===
> > > --- linux-pm.orig/kernel/sched/deadline.c
> > > +++ linux
In rrpc, some calculations using block ids assume only one LUN being
used. This is a problem when an Open-Channel SSD with multiple LUNs is
used. This patch modifies this calculations.
Signed-off-by: Javier González
---
drivers/lightnvm/rrpc.c | 5 +++--
drivers/lightnvm/rrpc.h | 9 +
2
Extract clocks and put it specific file to help with platform
autogeneration.
Signed-off-by: Michal Simek
---
arch/arm64/boot/dts/xilinx/zynqmp-ep108-clk.dtsi | 88
arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts | 1 +
arch/arm64/boot/dts/xilinx/zynqmp.dtsi
Use 64bit size cell format instead of 32bit for memory
description. Change 64bit sizes also for all others IPs.
Signed-off-by: Michal Simek
---
arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts | 2 +-
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 63 ++---
2 files changed, 3
No functional change.
Signed-off-by: Michal Simek
---
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index 200fb588d0f5..7bc65e
On 11/02/16 13:22, Luca Abeni wrote:
> Hi Juri,
>
> On Thu, 11 Feb 2016 12:12:57 +
> Juri Lelli wrote:
> [...]
> > I think we still have (at least) two problems:
> >
> > - select_task_rq_dl, if we select a different target
> > - select_task_rq might make use of select_fallback_rq, if
> > c
From: Daniel Chromik
There is an anonymous struct which is actually used as a bitmap. So
convert the struct to a bitmap and change code accordingly where
needed.
This also allows for a cleanup of set_data_bits and set_ctrl_bits as
they can use a common helper now. The helper can also be converte
On 02/11/2016 12:12 PM, Peter Ujfalusi wrote:
> On 02/11/2016 11:41 AM, Lars-Peter Clausen wrote:
>> On 02/11/2016 10:08 AM, Peter Ujfalusi wrote:
>>> We need the callback to support the dmaengine_terminate_sync().
>>>
>>> Signed-off-by: Peter Ujfalusi
>>
>> Looks good, but I noticed a slight race
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