On Wed, 2015-10-28 at 07:59 +0100, Thomas Hellstrom wrote:
> Kamal,
>
> On 10/27/2015 10:29 PM, Kamal Mostafa wrote:
> > 3.19.8-ckt9 -stable review patch. If anyone has any objections, please let
> > me know.
> >
> > --
> >
> > From: Thomas Hellstrom
> >
> > commit 54c12bc374408
On Wed, 2015-10-28 at 12:16 -0700, Kamal Mostafa wrote:
> On Wed, 2015-10-28 at 07:59 +0100, Thomas Hellstrom wrote:
> > Kamal,
> >
> > On 10/27/2015 10:29 PM, Kamal Mostafa wrote:
> > > 3.19.8-ckt9 -stable review patch. If anyone has any objections, please
> > > let me know.
> > >
> > > ---
On Wed, 2015-10-28 at 10:34 -0600, Toshi Kani wrote:
> On Wed, 2015-10-28 at 12:53 +0300, Stas Sergeev wrote:
> > 28.10.2015 03:04, Toshi Kani пишет:
> > > On Wed, 2015-10-28 at 07:37 +0900, Linus Torvalds wrote:
> > > > On Tue, Oct 27, 2015 at 11:05 PM, Stas Sergeev
> > > > wrote:
> > > > >
> >
On 10/28/2015 12:04 PM, Alex Smith wrote:
On 28 October 2015 at 18:57, Leonid Yegoshin wrote:
As I've explained the VDSO will only use the CP0 counter in the same
situations that the kernel would when it is the active clocksource.
Any issue that makes the counter unreliable affects the kernel
From: Aniroop Mathur
clk_type and clkid stores different predefined clock identification
values so they cannot be compared.
Therefore, lets fix it to avoid unexpected results.
Signed-off-by: Aniroop Mathur
Signed-off-by: Aniroop Mathur
---
drivers/input/evdev.c | 10 ++
1 file changed
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On Tue, 27 Oct 2015, Peter Zijlstra wrote:
On Wed, Oct 28, 2015 at 06:33:56AM +0900, Linus Torvalds wrote:
On Wed, Oct 28, 2015 at 4:53 AM, Davidlohr Bueso wrote:
>
> Note that this might affect callers that could/would rely on the
> atomicity semantics, but there are no guarantees of that for
On Wed, 28 Oct 2015, Steffen Trumtrar wrote:
> On Tue, Oct 27, 2015 at 05:09:11PM -0500, at...@opensource.altera.com wrote:
> > From: Alan Tull
> >
> > New bindings document for simple fpga bus.
> >
> > Signed-off-by: Alan Tull
> > ---
> > v9: initial version added to this patchset
> > v10: s
On Wed, Oct 28, 2015 at 11:32:14AM -0700, Alexander Duyck wrote:
> On 10/28/2015 09:37 AM, Bjorn Helgaas wrote:
> >Hi Alex,
> >
> >On Tue, Oct 27, 2015 at 01:52:21PM -0700, Alexander Duyck wrote:
> >>This patch forces us to reallocate VF BARs if the totalVFs value has
> >>increased after enabling A
On 28 October 2015 at 19:28, Leonid Yegoshin wrote:
> On 10/28/2015 12:04 PM, Alex Smith wrote:
>>
>> On 28 October 2015 at 18:57, Leonid Yegoshin
>> wrote:
>>>
>>>
>> As I've explained the VDSO will only use the CP0 counter in the same
>> situations that the kernel would when it is the active cl
Hi Yakir,
Am Mittwoch, 28. Oktober 2015, 16:26:33 schrieb Yakir Yang:
> diff --git a/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
> b/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
> index 7a3a9cd..9905081 100644
> --- a/Documentation/devicetree/bindings/display/
From: Mike Chan
This governor is designed for latency-sensitive workloads, such as
interactive user interfaces. The interactive governor aims to be
significantly more responsive to ramp CPU quickly up when CPU-intensive
activity begins.
Existing governors sample CPU load at a particular rate, t
On Wed, Oct 28, 2015 at 01:30:40PM -0300, Arnaldo Carvalho de Melo wrote:
> Hi Jiri, Wang,
>
> I'm getting these while doing 'make -C tools/perf build-test':
>
> LD fixdep-in.o
> LINK fixdep
> /bin/sh: /home/acme/git/linux/tools/build/fixdep: Permission denied
> make[6]: *** [
On 10/28/2015 12:55 PM, Alex Smith wrote:
On 28 October 2015 at 19:28, Leonid Yegoshin wrote:
.
Clocksources are not per-CPU. If the CP0 counter is the current
clocksource, then both the kernel and VDSO implementations of
gettimeofday will read out the CP0 counter from whatever CPU they run
on
From: Aniroop Mathur
clk_type and clkid stores different predefined clock identification
values so they cannot be compared for checking duplicate clock change
request. Therefore, lets fix it to avoid unexpected results.
Signed-off-by: Aniroop Mathur
Signed-off-by: Aniroop Mathur
---
drivers/i
Dan Williams writes:
> The DAX implementation needs to protect new calls to ->direct_access()
> and usage of its return value against unbind of the underlying block
> device. Use blk_queue_enter()/blk_queue_exit() to either prevent
> blk_cleanup_queue() from proceeding, or fail the dax_map_atomi
Dan Williams writes:
> Similar to the file_inode() helper, provide a helper to lookup the inode for a
> raw block device itself.
>
> Cc: Al Viro
> Suggested-by: Jan Kara
> Signed-off-by: Dan Williams
Reviewed-by: Jeff Moyer
> ---
> fs/block_dev.c | 19 ---
> 1 file chang
This patch is to the host_interface.c that fixes up following
warning by checkpatch:
-prefer eth_broadcast_addr() over memset()
Signed-off-by: Punit Vara
---
Applied on updated staging tree.
drivers/staging/wilc1000/host_interface.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff -
On 10/27/2015 05:16 PM, Rasmus Villemoes wrote:
I'm not familiar with this code, but path_info_show() (added in
8270b86243658 "hpsa: add sysfs entry path_info to show box and
bay information") seems to be broken in multiple ways.
First, there's
817 return snprintf(buf, output_len+1, "%s%s%s%
[..]
> I do not think it's a good fit for the socfpga, or for the lower level
> fpga drivers _in general_. Nor do I think that the FPGA Bridge
> framework, as written, is a good fit for fpgas in general.
Could you elaborate a bit more on why you feel that way? For all
configurations that I could
On Wednesday, October 28, 2015 09:40:34 AM Saurabh Sengar wrote:
> variavle rc in not required as it is just used for unchanged for return,
> and return is always 0 in the function.
>
> Signed-off-by: Saurabh Sengar
> ---
> kernel/audit.c | 7 +++
> 1 file changed, 3 insertions(+), 4 deletio
On 10/28/2015 09:33 AM, Ingo Molnar wrote:
* Tejun Heo wrote:
Subject: writeback: don't use list_entry_rcu() for pointer offsetting in
bdi_split_work_to_wbs()
bdi_split_work_to_wbs() uses list_for_each_entry_rcu_continue() to
walk @bdi->wb_list. To set up the initial iteration condition,
Hi Yakir,
Am Mittwoch, 28. Oktober 2015, 16:30:33 schrieb Yakir Yang:
> +static int rockchip_dp_phy_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct device_node *np = dev->of_node;
> + struct phy_provider *phy_provider;
> + struct rockchip_dp
Em Wed, Oct 28, 2015 at 09:13:52PM +0100, Jiri Olsa escreveu:
> On Wed, Oct 28, 2015 at 01:30:40PM -0300, Arnaldo Carvalho de Melo wrote:
> > Hi Jiri, Wang,
> >
> > I'm getting these while doing 'make -C tools/perf build-test':
> >
> > LD fixdep-in.o
> > LINK fixdep
> > /bin/sh:
On Wednesday, October 28, 2015 at 05:32:15 PM, Boris Brezillon wrote:
> Hi Marek,
Hi Boris,
> On Wed, 28 Oct 2015 17:11:14 +0100
>
> Marek Vasut wrote:
> > On Wednesday, October 28, 2015 at 08:58:13 AM, Boris Brezillon wrote:
> > > Hi Brian,
> >
> > Hi,
> >
> > [...]
> >
> > > > Are
> > > >
From: Greg Kroah-Hartman
As a result of the discussion at the 2015 Linux Kernel summit, the 4.4
kernel will be the next longterm kernel release, so notify everyone
about this on the web site.
Signed-off-by: Greg Kroah-Hartman
---
content/releases.rst | 1 +
1 file changed, 1 insertion(+)
diff
Charles Keepax writes:
>> @@ -1158,6 +1199,9 @@ static int wm9713_soc_suspend(struct snd_soc_codec
>> *codec)
>> {
>> u16 reg;
>>
>> +snd_soc_cache_sync(codec);
>
> There doesn't seem to be much point in syncing the cache at the
> start of a suspend, in theory I would expect the cach
On Wed, Oct 28, 2015 at 05:37:52PM -0300, Arnaldo Carvalho de Melo wrote:
> Em Wed, Oct 28, 2015 at 09:13:52PM +0100, Jiri Olsa escreveu:
> > On Wed, Oct 28, 2015 at 01:30:40PM -0300, Arnaldo Carvalho de Melo wrote:
> > > Hi Jiri, Wang,
> > >
> > > I'm getting these while doing 'make -C tools/pe
Hemant Kumar writes:
> Hi David,
>
>
> On 10/07/2015 09:41 PM, David Ahern wrote:
>> On 10/6/15 8:25 PM, Hemant Kumar wrote:
>>> @@ -358,7 +357,12 @@ static bool handle_end_event(struct
>>> perf_kvm_stat *kvm,
>>> time_diff = sample->time - time_begin;
>>>
>>> if (kvm->duration && tim
Hi Andres,
On Wed, Oct 28, 2015 at 10:27:52AM +0100, Andres Freund wrote:
> On 2015-10-25 08:39:12 +1100, Dave Chinner wrote:
> > Data integrity operations require related file metadata (e.g. block
> > allocation trnascations) to be forced to the journal/disk, and a
> > device cache flush iss
Dan Williams writes:
> If an application wants exclusive access to all of the persistent memory
> provided by an NVDIMM namespace it can use this raw-block-dax facility
> to forgo establishing a filesystem. This capability is targeted
> primarily to hypervisors wanting to provision persistent me
Allowing other subsystems to clobber the DR7 register is a bad idea
when debuggers are loaded. I realize that this piece of code was
written for perf monitors, and poor KGDB and KDB have to use this
interface to set and clear hardware breakpoints. Problem with this
architecture is that is you are
Commit-ID: b33e18f61bd18227a456016a77b1a968f5bc1d65
Gitweb: http://git.kernel.org/tip/b33e18f61bd18227a456016a77b1a968f5bc1d65
Author: Tejun Heo
AuthorDate: Tue, 27 Oct 2015 14:19:39 +0900
Committer: Ingo Molnar
CommitDate: Wed, 28 Oct 2015 13:17:30 +0100
fs/writeback, rcu: Don't use l
On Wed, 28 Oct 2015, Mike Kravetz wrote:
> On 10/27/2015 08:34 PM, Hugh Dickins wrote:
>
> Thanks for the detailed response Hugh. I will try to address your questions
> and provide more reasoning behind the use case and need for this code.
And thank you for your detailed response, Mike: that hel
Em Wed, Oct 28, 2015 at 09:44:50PM +0100, Jiri Olsa escreveu:
> On Wed, Oct 28, 2015 at 05:37:52PM -0300, Arnaldo Carvalho de Melo wrote:
> > Em Wed, Oct 28, 2015 at 09:13:52PM +0100, Jiri Olsa escreveu:
> > > On Wed, Oct 28, 2015 at 01:30:40PM -0300, Arnaldo Carvalho de Melo wrote:
> > > > Hi Jiri
Dan Williams writes:
> On Thu, Oct 22, 2015 at 1:48 PM, Jeff Moyer wrote:
>> Dan Williams writes:
>>
>>> Both, __dax_pmd_fault, and clear_pmem() were taking special steps to
>>> clear memory a page at a time to take advantage of non-temporal
>>> clear_page() implementations. However, x86_64 do
Brian Norris writes:
>> >
>> > Do some sorts of chipselects come into play here ? Ie. you can have one
>> > master
>> > with multiple NAND chips connected to it.
>>
>> Most NAND controllers support interacting with several chips (or
>> dies in case your chip embeds several NAND dies), but I ke
"Williams, Dan J" writes:
> The problem is that intervening call to cond_resched(). I later want to
> inject an rcu_read_lock()/unlock() pair to allow flushing active
> dax_map_atomic() usages at driver teardown time [1]. But, I think the
> patch stands alone as a cleanup outside of that admitt
This patchset removes elm address entry from omap4 hwmod and adds
an elm DT node to omap4.dtsi.
Since no omap4 supports nand in mainline this patchset was boot
tested on a pandaboard.
Franklin S Cooper Jr (2):
ARM: dts: omap4: Add elm node
ARM: omap4: hwmod: Remove elm address space from hwmo
ELM address information is provided by device tree. No longer need
to include this information within hwmod.
This patch has only been boot tested.
Signed-off-by: Franklin S Cooper Jr
---
arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 10 --
1 file changed, 10 deletions(-)
diff --git a/ar
This change is preparation for implementing a cp2108 bug workaround.
The workaround requires storing some private data. Right now the data is
attached to the USB interface and allocated in the attach() callback.
The bug detection requires USB I/O which is done easier from port_probe()
callback rath
Commit-ID: 78b9bc947b18ed16b6c2c573d774e6d54ad9452d
Gitweb: http://git.kernel.org/tip/78b9bc947b18ed16b6c2c573d774e6d54ad9452d
Author: Taku Izumi
AuthorDate: Fri, 23 Oct 2015 11:48:17 +0200
Committer: Ingo Molnar
CommitDate: Wed, 28 Oct 2015 12:28:06 +0100
efi: Fix warning of int-to-po
Commit-ID: 44511fb9e55ada760822b0b0d7be9d150576f17f
Gitweb: http://git.kernel.org/tip/44511fb9e55ada760822b0b0d7be9d150576f17f
Author: Ard Biesheuvel
AuthorDate: Fri, 23 Oct 2015 11:48:16 +0200
Committer: Ingo Molnar
CommitDate: Wed, 28 Oct 2015 12:28:06 +0100
efi: Use correct type for
Add device tree entry for the error location module.
Signed-off-by: Franklin S Cooper Jr
---
arch/arm/boot/dts/omap4.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 5a206c1..a40eb23 100644
--- a/arch/arm/boot/dts/
cp2108 GET_LINE_CTL returns the 16-bit value with the 2 bytes swapped.
However, SET_LINE_CTL functions properly. When the driver tries to modify
the register, it reads it, modifies some bits and writes back. Because the
read bytes were swapped, this often results in an invalid value to be
written.
Occasionally, writing data and immediately closing the port makes cp2108
stop responding. The device has to be unplugged to clear the error.
The failure is induced by shutting down the device while its Tx queue
still has unsent data. This condition is avoided by issuing PURGE command
from the close
On Mon, Oct 26, 2015 at 06:26:53PM -0700, Stephen Boyd wrote:
> These clocks are fixed rate board sources that should be in DT.
> Add them.
>
> Cc: Georgi Djakov
> Signed-off-by: Stephen Boyd
> ---
Reviewed-by: Andy Gross
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On 10/28/2015 02:00 PM, Hugh Dickins wrote:
> On Wed, 28 Oct 2015, Mike Kravetz wrote:
>> On 10/27/2015 08:34 PM, Hugh Dickins wrote:
>>
>> Thanks for the detailed response Hugh. I will try to address your questions
>> and provide more reasoning behind the use case and need for this code.
>
> And
This patch introduces the data structures and prototypes of functions
needed for doing AES CBC encryption using multi-buffer. Included are
the structures of the multi-buffer AES CBC job, job scheduler in C and
data structure defines in x86 assembly code.
Originally-by: Chandramouli Narayanan
Sig
In this patch series, we introduce AES CBC encryption that is parallelized
on x86_64 cpu with AVX2. The multi-buffer technique takes advantage
of wide AVX2 register and encrypt 8 data streams in parallel with SIMD
instructions. Decryption is handled as in the existing AESNI Intel CBC
implementatio
On 28/10/15 01:04, Mark Brown wrote:
> On Tue, Oct 27, 2015 at 01:55:27PM +, Damien Horsley wrote:
>> On 23/10/15 23:57, Mark Brown wrote:
>
>>> Shouldn't we be doing that flush on stream close instead? If nothing
>>> else the flush is going to discard a bit of data if the stream is just
>>>
In this patch, the infrastructure needed in support of multibuffer
encryption implementation is added:
a) Enhace mcryptd daemon to support blkcipher requests.
b) Update configuration to include multi-buffer encryption build support.
c) Add support to crypto scatterwalk that can sleep during enc
This patch introduces the multi-buffer job manager which is responsible
for submitting scatter-gather buffers from several AES CBC jobs
to the multi-buffer algorithm. The glue code interfaces with the
underlying algorithm that handles 8 data streams of AES CBC encryption
in parallel. AES key expan
This patch implements in-order scheduler for encrypting multiple buffers
in parallel supporting AES CBC encryption with key sizes of
128, 192 and 256 bits. It uses 8 data lanes by taking advantage of the
SIMD instructions with AVX2 registers.
The multibuffer manager and scheduler is mostly writte
This patch introduces the assembly routine to do a by8 AES CBC encryption
in support of the AES CBC multi-buffer implementation.
Encryption of 8 data streams of a key size are done simultaneously.
Originally-by: Chandramouli Narayanan
Signed-off-by: Tim Chen
---
arch/x86/crypto/aes-cbc-mb/aes
There is really no way to safely give a user full access to a DMA
capable device without an IOMMU to protect the host system. There is
also no way to provide DMA translation, for use cases such as device
assignment to virtual machines. However, there are still those users
that want userspace driv
Added sys-reboot node to the FSL's LS2085A SoC DT to leverage
the ARM-generic reboot mechanism for this SoC. This mechanism
is enabled through CONFIG_POWER_RESET_SYSCON.
Signed-off-by: J. German Rivera
---
CHANGE HISTORY
Changes in v2:
- Address comment form Stuart Yoder:
* Removed "@" from re
From: dcashman
ASLR currently only uses 8 bits to generate the random offset for the
mmap base address on 32 bit architectures. This value was chosen to
prevent a poorly chosen value from dividing the address space in such
a way as to prevent large allocations. This may not be an issue on all
pla
From: dcashman
arm: arch_mmap_rnd() uses a hard-code value of 8 to generate the
random offset for the mmap base address. This value represents a
compromise between increased ASLR effectiveness and avoiding
address-space fragmentation. Replace it with a Kconfig option, which
is sensibly bounded,
Hi Mike,
[auto build test ERROR on pm/linux-next -- if it's inappropriate base, please
suggest rules for selecting the more suitable base]
url:
https://github.com/0day-ci/linux/commits/B-lint-Czobor/cpufreq-interactive-New-interactive-governor/20151029-041207
config: i386-allmodconfig (attac
On Tue, 2015-10-27 at 11:32 -0500, Liberman Igal-B31950 wrote:
> > > +
> > > +struct device *fman_get_device(struct fman *fman) {
> > > + return fman->dev;
> > > +}
> >
> > Is this really necessary?
> >
>
> Fman port needs fman->dev, fman structure is opaque, so yes, it's needed.
Why is opacit
Davidlohr Bueso writes:
> This is really about simplifying the double xchg patterns into
> a single cmpxchg, with the same logic. Other than the immediate
> cleanup, there are some subtleties this change deals with:
>
> (i) While the load of the old bt is fully ordered wrt everything,
> ie:
>
>
On 10/28/2015 12:52 PM, Bjorn Helgaas wrote:
On Wed, Oct 28, 2015 at 11:32:14AM -0700, Alexander Duyck wrote:
On 10/28/2015 09:37 AM, Bjorn Helgaas wrote:
Hi Alex,
On Tue, Oct 27, 2015 at 01:52:21PM -0700, Alexander Duyck wrote:
This patch forces us to reallocate VF BARs if the totalVFs value
On Wed, Oct 28, 2015 at 03:21:45PM -0600, Alex Williamson wrote:
> There is really no way to safely give a user full access to a DMA
> capable device without an IOMMU to protect the host system. There is
> also no way to provide DMA translation, for use cases such as device
> assignment to virtual
On 10/28/2015 11:43 AM, Bjorn Helgaas wrote:
On Wed, Oct 28, 2015 at 11:32:16AM -0500, Bjorn Helgaas wrote:
Hi Alex,
Thanks a lot for cleaning this up. I think this is a great
improvement over what I did.
On Tue, Oct 27, 2015 at 01:52:15PM -0700, Alexander Duyck wrote:
This patch pulls the v
On Wed, Oct 28, 2015 at 12:18:48PM -0600, Alex Williamson wrote:
> On Wed, 2015-10-28 at 10:50 -0700, Yunhong Jiang wrote:
> > On Wed, Oct 28, 2015 at 01:44:55AM +0100, Paolo Bonzini wrote:
>
> It's in linux-next via the kvm.git next branch:
>
> git://git.kernel.org/pub/scm/virt/kvm/kvm.git
>
>
From: Mike Chan
This governor is designed for latency-sensitive workloads, such as
interactive user interfaces. The interactive governor aims to be
significantly more responsive to ramp CPU quickly up when CPU-intensive
activity begins.
Existing governors sample CPU load at a particular rate, t
This series implements the very slow but correct handling for
blkdev_issue_flush() with DAX mappings, as discussed here:
https://lkml.org/lkml/2015/10/26/116
I don't think that we can actually do the
on_each_cpu(sync_cache, ...);
...where sync_cache is something like:
cache_disable();
Make blkdev_issue_flush() behave correctly according to its required
semantics - all volatile cached data is flushed to stable storage.
Eventually this needs to be replaced with something much more precise by
tracking dirty DAX entries via the radix tree in struct address_space, but
for now this g
The function __arch_wb_cache_pmem() was already an internal implementation
detail of the x86 PMEM API, but this functionality needs to be exported as
part of the general PMEM API to handle the fsync/msync case for DAX mmaps.
Signed-off-by: Ross Zwisler
---
arch/x86/include/asm/pmem.h | 11 ++
> On Oct 27, 2015, at 4:49 AM, Peter Oberparleiter
> wrote:
>
> Writing a number to /sys/bus/scsi/devices//queue_ramp_up_period
> returns the value of that number instead of the number of bytes written.
> This behavior can confuse programs expecting POSIX write() semantics.
> Fix this by returni
On Wed, 2015-10-28 at 16:35 -0400, Paul Moore wrote:
> On Wednesday, October 28, 2015 09:40:34 AM Saurabh Sengar wrote:
> > variavle rc in not required as it is just used for unchanged for return,
> > and return is always 0 in the function.
[]
> Thanks, applied with some spelling corrections to the
Ulf Hansson writes:
> I am not sure if this issue is the same as been discussed earlier on
> the mmc list regarding "discard/erase".
>
> Anyway, there have been several attempts to fix bugs related to this.
> One of these discussion kind of pointed out a viable solution, but
> unfortunate no patc
Ross Zwisler writes:
> This series implements the very slow but correct handling for
> blkdev_issue_flush() with DAX mappings, as discussed here:
>
> https://lkml.org/lkml/2015/10/26/116
>
> I don't think that we can actually do the
>
> on_each_cpu(sync_cache, ...);
>
> ...where sync_cache is
On Wed, 28 Oct 2015, Tetsuo Handa wrote:
> Christoph Lameter wrote:
> > On Wed, 28 Oct 2015, Tejun Heo wrote:
> >
> > > The only thing necessary here is WQ_MEM_RECLAIM. I don't see how
> > > WQ_SYSFS and WQ_FREEZABLE make sense here.
> >
> I can still trigger silent livelock with this patchset ap
On 2015/10/28, 10:54, "lustre-devel on behalf of James Simmons"
wrote:
>From: James Simmons
>
>Cleanup all the unneeded white space in libcfs_hash.h.
>
>Signed-off-by: James Simmons
Minor note - it would be better to keep these two email addresses
consistent.
>struct cfs_hash_bd {
>- str
On 2015/10/28, 10:54, "lustre-devel on behalf of James Simmons"
wrote:
>From: James Simmons
>
>Final cleanup to make libcfs_hash.h completely kernel standard
>compliant.
>
>Signed-off-by: James Simmons
>---
> .../lustre/include/linux/libcfs/libcfs_hash.h | 16
>++--
> 1 files
-Original Message-
From: Intel-wired-lan [mailto:intel-wired-lan-boun...@lists.osuosl.org] On
Behalf Of Nicholas Krause
Sent: Saturday, October 17, 2015 9:21 AM
To: Kirsher, Jeffrey T
Cc: linux-kernel@vger.kernel.org; intel-wired-...@lists.osuosl.org;
net...@vger.kernel.org
Subject: [I
From: Mike Frysinger
Commit 63159f5dcccb3858d88aaef800c4ee0eb4cc8577 changed the types from
long to __kernel_long_t, but didn't add a linux/types.h include. Code
that tries to include this header directly breaks:
/usr/include/linux/mqueue.h:26:2: error: unknown type name '__kernel_long_t'
__k
On Wednesday, October 28, 2015 at 09:55:24 PM, Robert Jarzmik wrote:
> Brian Norris writes:
> >> > Do some sorts of chipselects come into play here ? Ie. you can have
> >> > one master with multiple NAND chips connected to it.
> >>
> >> Most NAND controllers support interacting with several chips
Existing default implementation of __div64_32() for 32-bit arches unfolds
into huge routine with tons of arithmetics like +, -, * and all of them
in loops. That leads to obvious performance degradation if do_div() is
frequently used.
Good example is extensive TCP/IP traffic.
That's what I'm gettin
These DMA APIs are replaced with the newer versions, which return
the enum dev_dma_attr. So, we can safely remove them.
Signed-off-by: Suravee Suthikulpanit
CC: Rafael J. Wysocki
---
drivers/base/property.c | 13 -
include/acpi/acpi_bus.h | 34 --
i
A device could have one of the following DMA attributes:
* DMA not supported
* DMA non-coherent
* DMA coherent
So, this patch introduces enum dev_dma_attribute. This will be used by
new APIs introduced in later patches.
Signed-off-by: Suravee Suthikulpanit
CC: Rafael J. Wysocki
CC:
This patch adds support for setting up PCI device DMA coherency from
ACPI _CCA object that should normally be specified in the DSDT node
of its PCI host bridge.
Signed-off-by: Suravee Suthikulpanit
Acked-by: Bjorn Helgaas
Reviewed-by: Hanjun Guo
CC: Rafael J. Wysocki
---
drivers/pci/probe.c |
On Wed, Oct 28, 2015 at 06:24:29PM -0400, Jeff Moyer wrote:
> Ross Zwisler writes:
>
> > This series implements the very slow but correct handling for
> > blkdev_issue_flush() with DAX mappings, as discussed here:
> >
> > https://lkml.org/lkml/2015/10/26/116
> >
> > I don't think that we can actu
In case of error, the current code return w/o calling
pci_put_host_bridge_device. This patch fixes this.
Signed-off-by: Suravee Suthikulpanit
Acked-by: Bjorn Helgaas
---
drivers/of/of_pci.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/of/of_pci.c b/drivers/of
On Wed, Oct 28, 2015 at 9:12 AM, Michael S. Tsirkin wrote:
> On Wed, Oct 28, 2015 at 11:32:34PM +0900, David Woodhouse wrote:
>> > I don't have a problem with extending DMA API to address
>> > more usecases.
>>
>> No, this isn't an extension. This is fixing a bug, on certain platforms
>> where the
This patch move of_pci_dma_configure() to a more generic
pci_dma_configure(), which can be extended by non-OF code (e.g. ACPI).
This has no functional change.
Signed-off-by: Suravee Suthikulpanit
Acked-by: Rob Herring
Acked-by: Bjorn Helgaas
Reviewed-by: Hanjun Guo
CC: Rafael J. Wysocki
---
To further improve the RDS connection scalabilty on massive systems
where number of sockets grows into tens of thousands of sockets, there
is a need of larger bind hashtable. Pre-allocated 8K or 16K table is
not very flexible in terms of memory utilisation. The rhashtable
infrastructure gives us t
Adding acpi_get_dma_attr() to query DMA attributes of ACPI devices.
It returns the enum dev_dma_attr, which communicates DMA information
more clearly. This API replaces the acpi_check_dma(), which will be
removed in subsequent patch.
This patch also provides a convenient function, acpi_dma_support
Now that we have the new DMA attribute APIs, we can replace the older
acpi_check_dma() and device_dma_is_coherent().
Signed-off-by: Suravee Suthikulpanit
CC: Rafael J. Wysocki
CC: Tom Lendacky
CC: Herbert Xu
CC: David S. Miller
---
drivers/acpi/acpi_platform.c | 7 ++-
driv
From: Jeremy Linton
ACPI configurations can now mark devices as noncoherent,
support that choice.
NOTE: This is required to support USB on ARM Juno Development Board.
Signed-off-by: Jeremy Linton
Signed-off-by: Suravee Suthikulpanit
CC: Bjorn Helgaas
CC: Catalin Marinas
CC: Rob Herring
CC:
This patch series adds support to setup DMA coherency for PCI device using
the ACPI _CCA attribute. According to the ACPI spec, the _CCA attribute
is required for ARM64. Therefore, this patch is a pre-req for ACPI PCI
support for ARM64 which is currently in development. Also, this should
not affec
On Wed, 2015-10-28 at 13:22 -0600, Toshi Kani wrote:
> On Wed, 2015-10-28 at 10:34 -0600, Toshi Kani wrote:
> > On Wed, 2015-10-28 at 12:53 +0300, Stas Sergeev wrote:
> > > 28.10.2015 03:04, Toshi Kani пишет:
> > > > On Wed, 2015-10-28 at 07:37 +0900, Linus Torvalds wrote:
> > > > > On Tue, Oct 27,
The function device_dma_is_coherent() does not sufficiently
communicate device DMA attributes. Instead, this patch introduces
device_get_dma_attr(), which returns enum dev_dma_attr.
It replaces the acpi_check_dma(), which will be removed in
subsequent patch.
This also provides a convenient functio
On Thu, Oct 29, 2015 at 7:24 AM, Jeff Moyer wrote:
> Ross Zwisler writes:
>
>> This series implements the very slow but correct handling for
>> blkdev_issue_flush() with DAX mappings, as discussed here:
>>
>> https://lkml.org/lkml/2015/10/26/116
>>
>> I don't think that we can actually do the
>>
On Wed, Oct 28, 2015 at 12:54:29PM -0400, James Simmons wrote:
> From: James Simmons
>
> Cleanup all the unneeded white space in libcfs_hash.h.
>
> Signed-off-by: James Simmons
> ---
> .../lustre/include/linux/libcfs/libcfs_hash.h | 147
> ++--
> 1 files changed, 73 inse
On Wed, Oct 28, 2015 at 12:54:31PM -0400, James Simmons wrote:
> From: James Simmons
>
> Cleanup all the unneeded white space in hash.c.
>
> Signed-off-by: James Simmons
> ---
> drivers/staging/lustre/lustre/libcfs/hash.c | 336
> ++-
> 1 files changed, 174 insertions
On Thu, Oct 29, 2015 at 7:09 AM, Ross Zwisler
wrote:
> Make blkdev_issue_flush() behave correctly according to its required
> semantics - all volatile cached data is flushed to stable storage.
>
> Eventually this needs to be replaced with something much more precise by
> tracking dirty DAX entries
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