GHES currently maps two pages with atomic_ioremap. From now
on, NMI is architectural depended so there is no need to allocate
an NMI page for platforms without NMI support.
To make it possible to not use a second page, swap the existing
page order so that the IRQ context page is first, and the op
Currently APEI depends on x86 architecture. It is because of NMI hardware
error notification of GHES which is currently supported by x86 only.
However, many other APEI features can be still used perfectly by other
architectures.
This commit adds two symbols:
1. HAVE_ACPI_APEI for those archs which
APEI is currently implemented so that it depends on x86 hardware.
The primary dependency is that GHES uses the x86 NMI for hardware
error notification and MCE for memory error handling. These patches
remove that dependency.
Other APEI features such as error reporting via external IRQ, error
serial
This commit abstracts MCE calls and provides weak corresponding default
implementation for those architectures which do not need arch specific
actions. Each platform willing to do additional architectural actions
should provides desired function definition. It allows us to avoid wrap
code into #ifd
On Tue, Jul 22, 2014 at 10:19 AM, Oded Gabbay wrote:
>> Exactly, just prevent userspace from submitting more. And if you have
>> misbehaving userspace that submits too much, reset the gpu and tell it
>> that you're sorry but won't schedule any more work.
>
> I'm not sure how you intend to know if
On Tue, Jul 22, 2014 at 11:21 AM, Daniel Vetter wrote:
> On Tue, Jul 22, 2014 at 10:19 AM, Oded Gabbay wrote:
>>> Exactly, just prevent userspace from submitting more. And if you have
>>> misbehaving userspace that submits too much, reset the gpu and tell it
>>> that you're sorry but won't schedu
ARM: DT: STi: STiH416: Add DT node for ST's SATA device
Cc: devicet...@vger.kernel.org
Acked-by: Alexandre Torgue
Signed-off-by: Lee Jones
diff --git a/arch/arm/boot/dts/stih416-b2020.dts
b/arch/arm/boot/dts/stih416-b2020.dts
index c3c2ac6..eb2f246 100644
--- a/arch/arm/boot/dts/stih416-b2
On Tue 2014-07-22 11:16:58, Rickard Strandqvist wrote:
> Hi
>
> Sure, I agree. But as I thought that I would not change
> currentfunctionality, I would increase the chance that the patches were
> included. And it would of course also clarify this type of problem.
I'm trying to say that getting ri
On Tue, Jul 22, 2014 at 04:46:41AM -0400, Chen, Gong wrote:
>On Tue, Jul 22, 2014 at 04:04:52PM +0800, Wanpeng Li wrote:
>> Subject: [PATCH v2] x86, hotplug: fix llc shared map unreleased during cpu
>> hotplug
>
>See this link:
>https://lkml.org/lkml/2014/7/17/78
Interesting, thanks for your poin
On 07/22/2014 11:28 AM, Lee Jones wrote:
ARM: DT: STi: STiH416: Add DT node for ST's SATA device
Cc: devicet...@vger.kernel.org
Acked-by: Alexandre Torgue
Signed-off-by: Lee Jones
Thanks for the fixup.
Patch added to my queue for v3.17
Regards,
Maxime
--
To unsubscribe from this list: se
On Tue 22-07-14 09:30:05, Peter Zijlstra wrote:
> On Tue, Jul 22, 2014 at 02:18:47PM +0900, Gioh Kim wrote:
> > Hello,
> >
> > This patch try to solve problem that a long-lasting page cache of
> > ext4 superblock disturbs page migration.
> >
> > I've been testing CMA feature on my ARM-based platf
Hi Jingoo,
Sorry for the delay in replying. Thanks for reviewing,
see my comments inline below: -
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
>
Signed-off-by: Lee Jones
---
arch/arm/configs/multi_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/multi_v7_defconfig
b/arch/arm/configs/multi_v7_defconfig
index 1a695a5..055949c 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_d
Signed-off-by: Lee Jones
---
arch/arm/configs/multi_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/multi_v7_defconfig
b/arch/arm/configs/multi_v7_defconfig
index 5348364..1a695a5 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_d
On Mon 2014-07-21 12:07:38, Steven Rostedt wrote:
> On Mon, 21 Jul 2014 16:43:24 +0200
> Petr Mládek wrote:
>
> > On Fri 2014-07-18 17:34:43, Petr Mládek wrote:
> > > On Wed 2014-07-16 12:43:56, Steven Rostedt wrote:
> > > > On Wed, 16 Jul 2014 10:58:04 +0200
> > > > Petr Mladek wrote:
> > > >
From: Thomas Gleixner
There are only a few callbacks which really care about FROZEN
vs. !FROZEN. No need to have extra states for this.
Publish the frozen state in an extra variable which is updated under
the hotplug lock and let the users interested deal with it w/o
imposing that extra state ch
On Tue, Jul 22, 2014 at 10:55:38AM +0200, Peter Zijlstra wrote:
> On Tue, Jul 22, 2014 at 03:23:29AM +0200, Rafael J. Wysocki wrote:
>
> > That turned out to be more challenging than I had thought initially.
> >
> > The last version I sent was almost OK, but it had some issues (like it could
> >
Hi Jonathan
On Tue, Jul 22, 2014 at 12:56 AM, Jonathan Davies
wrote:
>
>
> On 18/07/14 15:08, Peter Zijlstra wrote:
>>
>> On Fri, Jul 18, 2014 at 01:59:06PM +0100, Jonathan Davies wrote:
>>>
>>> The current implementation of idle_cpu only considers tasks that might be
>>> in the
>>> CPU's runqueu
Hi David,
On Tue, Jul 22, 2014 at 4:58 AM, David Rientjes wrote:
> On Thu, 17 Jul 2014, Max Filippov wrote:
>
>> From: Leonid Yegoshin
>>
>> Provide hooks that allow architectures with aliasing cache to align
>> mapping address of high pages according to their color. Such architectures
>> may en
On Tue, Jul 22, 2014 at 05:30:23PM +0800, Wanpeng Li wrote:
> On Tue, Jul 22, 2014 at 04:46:41AM -0400, Chen, Gong wrote:
> >On Tue, Jul 22, 2014 at 04:04:52PM +0800, Wanpeng Li wrote:
> >> Subject: [PATCH v2] x86, hotplug: fix llc shared map unreleased during cpu
> >> hotplug
> >
> >See this link
On Mon 2014-07-21 08:02:36, Alex Elder wrote:
> If a log record has LOG_PREFIX set, its predecessor record should be
> terminated if it was marked LOG_CONT.
>
> In devkmsg_read(), this condition was being ignored, which would
> lead to such records showing up combined when reading /dev/kmsg.
> Fix
On Tue, Jul 22, 2014 at 01:39:51PM +0900, Alexandre Courbot wrote:
> I also don't think that would do it - for many displays the power-on
> sequence is not as simple as "switch all the regulators on".
> Maybe what we would want is to have panel-simple allow panels to
> provide a "probe" callback
I am Mrs. Susan Patrick, suffering from cancerous ailment.I want you to
establish my husband money (35,000,000.00 GBP) to charity home for the upkeep
of widows, widowers, orphans,destitute, the down-trodden, physically challenged
children. My Doctor told me recently, that I have limited days to
Enabling GENERIC_PHY in the shared (by most ARM sub-architectures)
defconfig multi_v7_defconfig is prohibited. Instead, we'll enable
it from the Kconfig whenever PHY_MIPHY365X is enabled.
Cc: Kishon Vijay Abraham I
Signed-off-by: Lee Jones
---
drivers/phy/Kconfig | 2 +-
1 file changed, 1 inse
On Mon, Jul 21, 2014 at 06:52:12PM +0200, Peter Zijlstra wrote:
> On Mon, Jul 21, 2014 at 11:35:28AM -0500, Bruno Wolff III wrote:
> > Is there more I can do to help with this now? Or should I just wait for
> > patches to test?
>
> Yeah, sorry, was wiped out today. I'll go stare harder at the P4
>
Hello,
On Di, 2014-07-22 at 00:44 -0400, Theodore Ts'o wrote:
> On Tue, Jul 22, 2014 at 03:02:20AM +0200, Hannes Frederic Sowa wrote:
> >
> > Ted, would it make sense to specifiy a 512 byte upper bound limit for
> > random entropy extraction (I am not yet convinced to do that for
> > urandom) and
On 22/07/14 12:21, Daniel Vetter wrote:
On Tue, Jul 22, 2014 at 10:19 AM, Oded Gabbay wrote:
Exactly, just prevent userspace from submitting more. And if you have
misbehaving userspace that submits too much, reset the gpu and tell it
that you're sorry but won't schedule any more work.
I'm not
Am 2014-07-22 04:22, schrieb Shawn Guo:
> On Fri, Jul 18, 2014 at 07:01:37PM +0200, Stefan Agner wrote:
>> This adds USB PHY and USB controller nodes. Vybrid SoCs have two
>> independent USB cores which each supports DR (dual role). However,
>> real OTG is not supported since the OTG ID pin is not
On Tue, 22 Jul 2014, Peter Zijlstra wrote:
> On Tue, Jul 22, 2014 at 10:39:17AM +0200, Thomas Gleixner wrote:
> > On Tue, 22 Jul 2014, Peter Zijlstra wrote:
> > > Anyway, there is one big fail in the entire futex stack that we 'need'
> > > to sort some day and that is NUMA. Some people (again datab
On Tue, 2014-07-08 at 14:06 +0100, Pawel Moll wrote:
> On Tue, 2014-06-24 at 12:55 +0100, Pawel Moll wrote:
> > This patch adds basic DT bindings for the PL11x CLCD cells
> > and make their fbdev driver use them.
> >
> > Signed-off-by: Pawel Moll
>
> As two weeks passed without any further comme
Hi Gu,
Investigation shows, that f2fs_evict_inode, when called for 'meta_inode', uses
invalidate_mapping_pages() for 'node_inode'.
But 'node_inode' is deleted before 'meta_inode' in f2fs_put_super via iput().
It seems that in common usage scenario this use-after-free is benign, because
'node_
On 07/22/2014 02:38 PM, Subbaraya Sundeep Bhatta wrote:
+#include
+#include
+#include
+#include "gadget_chips.h"
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
Normally we will put the includes in alphabetical because it looks
On Mon 2014-07-21 08:02:34, Alex Elder wrote:
> Each log record has a "flags" field. The flags keep track of, for
> instance, whether the record was saved in its entirety (as opposed
> to being one of multiple records that should be merged as a single
> unit). A log record's flags field alone is
On 07/22/2014 10:07 AM, Hugh Dickins wrote:
On Mon, 21 Jul 2014, Sasha Levin wrote:
On 07/19/2014 07:44 PM, Hugh Dickins wrote:
Otherwise, I've been unable to reproduce the shmem_fallocate hang.
Great. Andrew, I think we can say that it's now safe to send
1/2 shmem: fix faulting into a hole,
Hi,
Do you know if all these timings will be used by the nand drivers ?
I did a similar patch [1] (that wasn't merged :( ), and I used reduced
timing info.
I also have support for the omap driver
(http://article.gmane.org/gmane.linux.ports.arm.omap/88606/match=) and
a controller we use in our c
Hi Brian,
On Mon, Jul 14, 2014 at 12:19:47PM -0700, Brian Norris wrote:
> Hi Michael,
>
> On Fri, Jun 27, 2014 at 12:38:44PM +0200, Michael Grzeschik wrote:
> > The current approach of the read_page function is to iterate over all
> > subpages and call the correct_data function. The correct_data
Hi Arnd, Kevin, Olof,
On Fri, 2014-07-11 at 16:06 +0100, Pawel Moll wrote:
> Driver providing perf backend for ARM Cache Coherent Network
> interconnect. Supports counting all hardware events and crosspoint
> watchpoints.
>
> Currently works with CCN-504 only, although there should be
> no chang
kfree.cocci currently triggers on constructs like
(resending with proper CC list and subject line)
drivers/staging/rts5208/spi.c
596if (retval < 0) {
597kfree(buf);
598rtsx_clear_spi_error(chip);
599spi_set_err_code(chip, SPI_HW_ERR);
600TRACE_R
On Thursday 17 July 2014 01:19 PM, Tony Lindgren wrote:
> We seem to have this layout WR_SOFT_RESET and WR_CONTROL in the TRM:
>
> WR_SOFT_RESET
> [0] SOFT_RESET
>
> WR_CONTROL
> [3:2] MMR_STDBYMODE 0 = force-idle, 1 = no-standby
> [1:0] MMR_IDLEMODE0 = force-idle, 1 = no-idle
>
> And
On 21/07/14 17:46, Russell King - ARM Linux wrote:
> On Mon, Jul 21, 2014 at 03:47:16PM +0100, Daniel Thompson wrote:
>> From: Marek Vasut
>>
>> Add new device type, MT_DEVICE_NS. This type sets the NS bit in L1 PTE [1].
>> Accesses to a memory region which is mapped this way generate non-secure
>
> Thanks for reviewing, see my comments inline below: -
In future, it's best to only reply to questions, or review comments
that you disagree with. Anything that you will action or agree with
can be snipped along with any irrelevant code from your reply and
replaced with "" or "[...]". If you ar
On Tue, 2014-07-22 at 09:50 +0800, Ethan Zhao wrote:
> There is global funcion pci_vfs_assigned(), so use it instead of
> composing
> local one.
>
> Signed-off-by: Ethan Zhao
> ---
> drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c | 31
> +---
> 1 files changed, 1 insertions
On Sunday 20 July 2014 17:45:40 Chen Gang wrote:
> >
> > Next, I shall:
> >
> > - Remove HAS_IOMEM and NO_IOMEM from kernel, firstly.
> >
> > - Try to make dummy IOMEM functions for score architecture.
> >
> > - Continue discussing with UML for it.
> >
>
> Oh, sorry, I forgot, after remove
On Thu, 17 Jul 2014, Stanimir Varbanov wrote:
> The pm8921-core driver presently supports pm8921 and pm8058
> Qualcomm PMICs. To avoid confusion with new generation PMICs
> (like pm8941) rename the pm8921-core driver to more
> appropriate name pm8xxx-ssbi, which reflects better that
> those chips
On Tue, Jul 22, 2014 at 02:41:29AM +0200, Rafael J. Wysocki wrote:
> It looks like some specific need motivated the Joerg's work, however,
> so let's just not dismiss the use case lightly without knowing it.
The motivation was to optimize the data structures for machines with
large amounts of RAM
On Tue, Jul 22, 2014 at 11:47:40AM +0200, Peter Zijlstra wrote:
> On Mon, Jul 21, 2014 at 06:52:12PM +0200, Peter Zijlstra wrote:
> > On Mon, Jul 21, 2014 at 11:35:28AM -0500, Bruno Wolff III wrote:
> > > Is there more I can do to help with this now? Or should I just wait for
> > > patches to test?
Changes to the AIF configuration registers only take
effect when the AIF is disabled. If the configuration
is being changed from the previous setup, temporarily
disable the AIF.
Signed-off-by: Dimitris Papastamos
Signed-off-by: Richard Fitzgerald
---
sound/soc/codecs/arizona.c | 87 ++
Am Dienstag, 22. Juli 2014, 10:39:38 schrieb Arnd Bergmann:
> On Tuesday 22 July 2014 11:11:14 Chanwoo Choi wrote:
> > This patch add support for s3c2410/s3c2416/s3c2440/s3c2443 ADC. The
> > s3c24xx
> > is alomost same as ADCv1. But, There are a little difference as following:
> > - ADCMUX register
Goede dag,
We zijn Diamond Zwitserse lening bedrijf het geven van leningen
per post advertentie. Wij bieden verschillende soorten leningen (korte
en lange termijn leningen, persoonlijke leningen, leningen aan
bedrijven, enz.) met 3% rente. Wij geven leningen aan mensen in nood
Different playback and capture bits-per-sample
are not supported on the AIFs
Signed-off-by: Richard Fitzgerald
---
sound/soc/codecs/wm5110.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/sound/soc/codecs/wm5110.c b/sound/soc/codecs/wm5110.c
index 62ef544..2f2ec26 100
Different playback and capture bits-per-sample
are not supported on the AIFs
Signed-off-by: Richard Fitzgerald
---
sound/soc/codecs/wm5102.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/sound/soc/codecs/wm5102.c b/sound/soc/codecs/wm5102.c
index fa24d55..f602349 100
Different playback and capture bits-per-sample
are not supported on the AIFs
Signed-off-by: Richard Fitzgerald
---
sound/soc/codecs/wm8997.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/sound/soc/codecs/wm8997.c b/sound/soc/codecs/wm8997.c
index bb9b47b..ab33fe5 1006
>From c8a190816725dd6586bc9de997bf8e50416da428 Mon Sep 17 00:00:00 2001
From: Yuan Juntao
Date: Tue, 22 Jul 2014 18:16:34 +0800
Subject: [PATCH] Add SDR12 & SDR25 support for sdio cards.
According to SDIO simplified specification v3.0, a card should also
support SDR25 & SDR12 if one of the DDR50,
On Tue 2014-07-22 12:34:44, Joerg Roedel wrote:
> On Tue, Jul 22, 2014 at 02:41:29AM +0200, Rafael J. Wysocki wrote:
> > It looks like some specific need motivated the Joerg's work, however,
> > so let's just not dismiss the use case lightly without knowing it.
>
> The motivation was to optimize t
From: Sachin Kamat
PTR_ERR_OR_ZERO simplifies the code.
Signed-off-by: Sachin Kamat
Cc: Sylwester Nawrocki
Acked-by: Hans de Goede
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/phy-exynos-mipi-video.c |5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/driver
From: Sachin Kamat
Since the USB 2.0 PHYs are required with EHCI/OHCI USB drivers and
USB gadget controller supported by the DWC2 gadget driver, make it
depend on them and default to ARCH_EXYNOS as they are meant for
Exynos platforms. Also, make the sub-drivers silent options enabling
them based
Hi Greg,
Here's the PULL Request for 3.17 merge window. It adds regulator
support in PHY core and adds better support for multi-phy PHY providers.
It includes a bunch of new PHY drivers and some misc cleanups and fixes.
Let me know if I have to change something.
Cheers
Kishon
The following chan
From: Marek Szyprowski
This patch adds support for Exynos3250 SoC to Exynos2USB PHY driver.
Although Exynos3250 has only one device phy interface, the register
layout and all operations that are required to get it enabled are almost
same as on Exynos4x12. The only different is one more register
(
From: Lee Jones
The MiPHY365x is a Generic PHY which can serve various SATA or PCIe
devices. It has 2 ports which it can use for either; both SATA, both
PCIe or one of each in any configuration.
Acked-by: Mark Rutland
Acked-by: Alexandre Torgue
Signed-off-by: Lee Jones
Signed-off-by: Kishon V
On Tue 2014-07-22 12:34:44, Joerg Roedel wrote:
> On Tue, Jul 22, 2014 at 02:41:29AM +0200, Rafael J. Wysocki wrote:
> > It looks like some specific need motivated the Joerg's work, however,
> > so let's just not dismiss the use case lightly without knowing it.
>
> The motivation was to optimize t
From: Srinivas Kandagatla
This patch fixes a possible timeout in poll loop without actually
checking the register before return. In theory the there is a possibility
of loop being scheduled after a long lock/delay, which would then force
the loop to exit without actually checking the register.
R
From: Antoine Ténart
The Berlin SATA PHY drives the PHY related to the SATA interface. Add
the corresponding documentation.
Signed-off-by: Antoine Ténart
Signed-off-by: Kishon Vijay Abraham I
---
.../devicetree/bindings/phy/berlin-sata-phy.txt| 34
1 file changed, 3
From: Lee Jones
The MiPHY365x is a Generic PHY which can serve various SATA or PCIe
devices. It has 2 ports which it can use for either; both SATA, both
PCIe or one of each in any configuration.
Acked-by: Mark Rutland
Signed-off-by: Alexandre Torgue
Signed-off-by: Lee Jones
Signed-off-by: Kis
From: Lee Jones
This has the added advantages of being able to enable/disable each
of the channels as simply as enabling/disabling the DT node.
Suggested-by: Kishon Vijay Abraham I
Signed-off-by: Lee Jones
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/phy-miphy365x.c | 256 +
In case of multi-phy PHY providers, each PHY should be modeled as a sub
node of the PHY provider. Then each PHY will have a different node pointer
(node pointer of sub node) than that of PHY provider. Added this provision
in the PHY core.
Also fixed all drivers to use the updated API.
Signed-off-b
Fixed of_phy_provider_lookup to return 'phy_provider' if _of_phy_get
passes the node pointer of the sub-node of phy provider node. This is
needed when phy provider implements multiple PHYs and each PHY is
modelled as the sub-node of PHY provider device node.
Signed-off-by: Kishon Vijay Abraham I
From: Kumar Gala
Add a PHY driver for uses with AHCI based SATA controller driver on the
IPQ806x family of SoCs.
Signed-off-by: Kumar Gala
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/Kconfig |7 ++
drivers/phy/Makefile|1 +
drivers/phy/phy-qco
From: Kumar Gala
Add binding spec for Qualcomm SoC PHYs, starting with the SATA PHY on
the IPQ806x family of SoCs.
Signed-off-by: Kumar Gala
Signed-off-by: Kishon Vijay Abraham I
---
.../bindings/phy/qcom-ipq806x-sata-phy.txt | 23
1 file changed, 23 insertions(
From: Srinivas Kandagatla
This patch adds binding spec for Qualcomm AP8064 SATA PHY.
Signed-off-by: Srinivas Kandagatla
Tested-by: Kiran Padwal
Signed-off-by: Kishon Vijay Abraham I
---
.../bindings/phy/qcom-apq8064-sata-phy.txt | 24
1 file changed, 24 inserti
From: Roger Quadros
Some PHYs can be powered by an external power regulator.
e.g. USB_HS PHY on DRA7 SoC. Make the PHY core support a
power regulator.
Signed-off-by: Roger Quadros
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/phy-core.c | 26 ++
include/linu
From: Sachin Kamat
USB DWC3 driver on Exynos platform does not work without its
corresponding phy driver. Hence make the PHY driver depend on
Exynos DWC3 driver and default it to yes to make things easier
for the end user.
Signed-off-by: Sachin Kamat
Reviewed-by: Jingoo Han
Tested-by: Vivek Ga
At the start of the intcall function, the %al register is compared to
0x3f. If it does not equal 0x3f it is equated to it. Instruction flow
continues in both cases from the label 1. The comparison is therefore
unneeded.
Testing data is appended.
Signed-off-and-tested-by: Klemen Jan Enova
---
From: Srinivas Kandagatla
Add a PHY driver for uses with AHCI based SATA controller driver on the
APQ8064 family of SoCs.
This patch is a forward port from Qualcomm's v3.4 andriod kernel.
Tested on IFC6410 board.
CC: Sujit Reddy Thumma
Tested-by: Kiran Padwal
Signed-off-by: Srinivas Kandagat
From: Andrew Lunn
mach-kirkwood has been removed, now that kirkwood lives in mach-mvebu.
Depend on MACH_KIRKWOOD, which will be set when these SoCs are built
as part of mach-mvebv.
Signed-off-by: Andrew Lunn
Cc: Kishon Vijay Abraham I
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/Kco
From: Roger Quadros
phy-supply is a phandle to the regulator that provides power to the
PHY. This regulator is managed during the PHY power on/off sequence
by the phy core driver.
Signed-off-by: Roger Quadros
Signed-off-by: Kishon Vijay Abraham I
---
.../devicetree/bindings/phy/phy-bindings.t
From: Antoine Ténart
The Berlin SoC has a two SATA ports. Add a PHY driver to handle them.
The mode selection can let us think this PHY can be configured to fit
other purposes. But there are reasons to think the SATA mode will be
the only one usable: the PHY registers are only accessible indirec
From: Jingoo Han
Make local functions static, because these are used only in this
file.
Signed-off-by: Jingoo Han
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/phy-exynos5-usbdrd.c |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/phy-exynos5-usb
From: Jiancheng Xue
Add necessary binding documentation SATA PHY on Hisilicon hix5hd2 soc.
Signed-off-by: Jiancheng Xue
Signed-off-by: Zhangfei Gao
Signed-off-by: Kishon Vijay Abraham I
---
.../devicetree/bindings/phy/hix5hd2-phy.txt| 22
1 file changed, 22 ins
On Thu, 17 Jul 2014, Stanimir Varbanov wrote:
> From: Josh Cartwright
>
> The Qualcomm SPMI PMIC chips are components used with the
> Snapdragon 800 series SoC family. This driver exists
> largely as a glue mfd component, it exists to be an owner
> of an SPMI regmap for children devices describ
From: Lee Jones
This provides the shared header file which will be reference from both
the MiPHY365x driver and its associated Device Tree node(s).
Cc: Kishon Vijay Abraham I
Acked-by: Mark Rutland
Acked-by: Alexandre Torgue
Signed-off-by: Lee Jones
Signed-off-by: Kishon Vijay Abraham I
---
From: Sachin Kamat
PTR_ERR_OR_ZERO simplifies the code.
Signed-off-by: Sachin Kamat
Cc: Jingoo Han
Acked-by: Hans de Goede
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/phy-exynos-dp-video.c |5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/phy-
8-bit delay value (0xF1) is required for GEN2 devices to be enumerated
consistently. Added an API to be called from PHY drivers to set this delay
value and called it from PIPE3 driver to set the delay value.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Roger Quadros
---
Documentation/devi
PCIe PHY uses an external pll instead of the internal pll used by SATA
and USB3. So added support in pipe3 PHY to use external pll.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Roger Quadros
---
Documentation/devicetree/bindings/phy/ti-phy.txt | 11 ++-
drivers/phy/phy-ti-pipe3.c
From: Kamil Debski
The Exynos4412 USB 2.0 PHY hardware differs from the description provided
in the documentation. Some register bits have different function. This
patch fixes the defines of register bits and changes the way how phys are
powered on and off.
Signed-off-by: Kamil Debski
Tested-by
From: Jiancheng Xue
Add hix5hd2-sata-phy driver on Hisilicon hix5hd2 soc.
Signed-off-by: Jiancheng Xue
Signed-off-by: Zhangfei Gao
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/Kconfig|8 ++
drivers/phy/Makefile |1 +
drivers/phy/phy-hix5hd2-sata.c | 19
From: Sachin Kamat
PTR_ERR_OR_ZERO simplifies the code.
Signed-off-by: Sachin Kamat
Cc: Maxime Ripard
Acked-by: Hans de Goede
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/phy-sun4i-usb.c |5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/phy-sun
On Tue, Jul 22, 2014 at 12:35:57AM -0400, Pranith Kumar wrote:
> Hi Paul,
>
> I was going through this code and found a few inconsistencies. I git blamed it
> and found that it was this recent commit and thought I could ask a few
> questions. I am dropping the CC's as I am not sure since it is pre
On Tue, Jul 22, 2014 at 12:52:40AM -0400, Pranith Kumar wrote:
> Doh! I figured it out *after* I sent out the mail. Sorry for the noise!
I know that feeling! ;-)
Thanx, Paul
> On Tue, Jul 22, 2014 at 12:35 AM, Pranith Kumar wrote:
> > Hi
Looks like the default location for TI firmware is inside the ti-connectivity
directory, to be coherent with other firmware request used by TI drivers, load
the TIInit firmware from this directory instead of /lib/firmware directly.
Signed-off-by: Enric Balletbo i Serra
---
drivers/misc/ti-st/st_
This is part of an effort to clean-up the MFD subsystem.
WARNING: Missing a blank line after declarations
+ struct lp8788_irq_data *irqd = irq_data_get_irq_chip_data(data);
+ irqd->enabled[data->hwirq] = 1;
WARNING: Missing a blank line after declarations
+ struct lp8788_irq_dat
This is part of an effort to clean-up the MFD subsystem.
WARNING: line over 80 characters
+ { 0x0068, 0x01FF },/* R104 - Always On Triggers Sequence
Select 3 */
WARNING: line over 80 characters
+ { 0x0069, 0x01FF },/* R105 - Always On Triggers Sequence
Select 4 *
This is part of an effort to clean-up the MFD subsystem.
WARNING: Missing a blank line after declarations
+ unsigned long flags;
+ spin_lock_irqsave(&mcp->lock, flags);
total: 0 errors, 1 warnings, 238 lines checked
Signed-off-by: Lee Jones
---
drivers/mfd/mcp-core.c | 1 +
1 file
This is part of an effort to clean-up the MFD subsystem.
WARNING: please, no space before tabs
+^IRSV_INTR_OFFSET, ^I/* Bit 12^IReserved^I^I*/$
WARNING: Missing a blank line after declarations
+ u8 unmask_value;
+ ret = twl_i2c_read_u8(TWL_MODULE_PIH, &unmask_value,
WARNING: Missing
This is part of an effort to clean-up the MFD subsystem.
ERROR: space required before the open parenthesis '('
+ if(!micro->msg)
WARNING: unnecessary whitespace before a quoted newline
+ dev_dbg(micro->dev, "key message ignored, no handle
\n");
WARNIN
This is part of an effort to clean-up the MFD subsystem.
WARNING: line over 80 characters
+struct si476x_rsq_status_args *rsqargs,
WARNING: line over 80 characters
+struct si476x_rsq_status_report *report)
WARNING: Unnecessary space before function
This is part of an effort to clean-up the MFD subsystem.
WARNING: braces {} are not necessary for single statement blocks
+ if (!iomem) {
+ return -EINVAL;
+ }
WARNING: sizeof *tc6387xb should be sizeof(*tc6387xb)
+ tc6387xb = kzalloc(sizeof *tc6387xb, GFP_KERNEL);
WARNING: line over 80 characters
+module_param_string(force_device_id, force_device_id, sizeof(force_device_id),
0);
WARNING: msleep < 20ms can sleep for up to 20ms; see
Documentation/timers/timers-howto.txt
+ msleep(1);
WARNING: __initdata should be placed after kempld_dmi_table[
This is part of an effort to clean-up the MFD subsystem.
WARNING: Missing a blank line after declarations
+ struct max8925_chip *chip = irq_data_get_irq_chip_data(data);
+ max8925_irqs[data->irq - chip->irq_base].enable
WARNING: Missing a blank line after declarations
+ struct m
This is part of an effort to clean-up the MFD subsystem.
WARNING: Missing a blank line after declarations
+ const struct of_device_id *match;
+ match = of_match_node(sec_dt_match, i2c->dev.of_node);
total: 0 errors, 1 warnings, 494 lines checked
Signed-off-by: Lee Jon
This is part of an effort to clean-up the MFD subsystem.
ERROR: space required after that ',' (ctx:VxO)
+ 0, &twl6040_irq_chip,&twl6040->irq_data);
^
ERROR: space required before that '&' (ctx:OxV)
+
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