; MMP clk drivers do so. I guess the initialization should look like any
> >>>> of the qcom GCC drivers then?
> >>>
> >>> Yes.
> >>
> >> With the entire clock driver code in one file this is quite messy as I also
> >> needed to add module_ini
river?
Not that I know of, I did it like this only because the other in-tree
MMP clk drivers do so. I guess the initialization should look like any
of the qcom GCC drivers then?
Yes.
With the entire clock driver code in one file this is quite messy as I also
needed to add module_init and module
a platform driver?
> > >
> > > Not that I know of, I did it like this only because the other in-tree
> > > MMP clk drivers do so. I guess the initialization should look like any
> > > of the qcom GCC drivers then?
> >
> > Yes.
>
> With the
it like this only because the other in-tree
> > MMP clk drivers do so. I guess the initialization should look like any
> > of the qcom GCC drivers then?
>
> Yes.
With the entire clock driver code in one file this is quite messy as I also
needed to add module_init and mod
Quoting Duje Mihanović (2024-04-11 03:15:34)
> On 4/11/2024 10:00 AM, Stephen Boyd wrote:
> >
> > Is there a reason this file can't be a platform driver?
>
> Not that I know of, I did it like this only because the other in-tree
> MMP clk drivers do so. I guess the initialization should look like
On 4/11/2024 10:00 AM, Stephen Boyd wrote:
Quoting Duje Mihanović (2024-04-02 13:55:41)
diff --git a/drivers/clk/mmp/clk-of-pxa1908.c b/drivers/clk/mmp/clk-of-pxa1908.c
new file mode 100644
index ..6f1f6e25a718
--- /dev/null
+++ b/drivers/clk/mmp/clk-of-pxa1908.c
@@ -0,0 +1,328 @@
+/
Quoting Duje Mihanović (2024-04-02 13:55:41)
> diff --git a/drivers/clk/mmp/clk-of-pxa1908.c
> b/drivers/clk/mmp/clk-of-pxa1908.c
> new file mode 100644
> index ..6f1f6e25a718
> --- /dev/null
> +++ b/drivers/clk/mmp/clk-of-pxa1908.c
> @@ -0,0 +1,328 @@
> +// SPDX-License-Identifier: GP
Add driver for Marvell PXA1908 clock controller blocks. The SoC has
numerous clock controller blocks, currently supporting APBC, APBCP, MPMU
and APMU.
Signed-off-by: Duje Mihanović
---
drivers/clk/mmp/Makefile | 2 +-
drivers/clk/mmp/clk-of-pxa1908.c | 328 +
Add driver for Marvell PXA1908 clock controller blocks. The SoC has
numerous clock controller blocks, currently supporting APBC, APBCP, MPMU
and APMU.
Signed-off-by: Duje Mihanović
---
drivers/clk/mmp/Makefile | 2 +-
drivers/clk/mmp/clk-of-pxa1908.c | 328 +
From: Gabriel Fernandez
RCC clock and reset controller shared same memory mapping.
As RCC clock driver is now a module, the best way to register clock
and reset controller is to do it in same driver.
Signed-off-by: Gabriel Fernandez
---
drivers/clk/clk-stm32mp1.c | 157
Quoting Sergio Paracuellos (2021-04-09 22:50:56)
> The documentation for this SOC only talks about two
> registers regarding to the clocks:
> * SYSC_REG_CPLL_CLKCFG0 - provides some information about
> boostrapped refclock. PLL and dividers used for CPU and some
> sort of BUS.
> * SYSC_REG_CPLL_CLK
On Mon 12 Apr 2021 at 22:27, Stephen Boyd wrote:
> Quoting Jerome Brunet (2021-04-10 04:13:54)
>> Clock drivers ops should not the clk API but the clock provider (clk_hw)
>> instead.
>>
>> Signed-off-by: Jerome Brunet
>> ---
>> sound/soc/codecs/rt5682.c | 6 +++---
>> 1 file changed, 3 inser
Quoting Jerome Brunet (2021-04-10 04:13:54)
> Clock drivers ops should not the clk API but the clock provider (clk_hw)
> instead.
>
> Signed-off-by: Jerome Brunet
> ---
> sound/soc/codecs/rt5682.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/sound/soc/codecs/rt
Clock drivers ops should not the clk API but the clock provider (clk_hw)
instead.
Signed-off-by: Jerome Brunet
---
sound/soc/codecs/rt5682.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/sound/soc/codecs/rt5682.c b/sound/soc/codecs/rt5682.c
index 0e2a10ed11da..2eee02a
s/clk/samsung/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 9b582b3fca34..5f06879d7fe9 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -100,6 +100,7 @@ obj-$(CONFIG_COMMON_CLK_NXP)+= nxp/
obj-$(CONFIG_MACH_PISTACHIO) += pistachio/
k_priv' struct to store there pointers to regmap handlers
to be able to use regmap operations from normal clock api functions. Add
this pointer in 'mt7621_clk' and 'mt7621_clk_gate' before register its
related clocks to make things work.
- Add Greg's Acked-by in pat
t;drivers/clk/samsung/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 5325847469e9..1b35ad852721 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -98,6 +98,7 @@ obj-$(CONFIG_COMMON_CLK_NXP) += nxp/
obj-$(CONFIG_MACH_PISTACHIO) += pistachio/
om normal clock api functions. Add
this pointer in 'mt7621_clk' and 'mt7621_clk_gate' before register its
related clocks to make things work.
- Add Greg's Acked-by in patches 4 and 5.
- Rebase this series on the top of linux-next tag 'next-20210215'.
l
> > +++ b/drivers/clk/ralink/Kconfig
> > @@ -0,0 +1,15 @@
> > +# SPDX-License-Identifier: GPL-2.0-only
> > +#
> > +# MediaTek Mt7621 Clock Driver
> > +#
> > +menu "Clock driver for Mediatek mt7621 SoC"
> > + depends on SOC_MT7621 || COMPIL
Quoting Sergio Paracuellos (2021-04-09 11:25:24)
> Hi Stephen,
>
> On Fri, Apr 9, 2021 at 8:17 PM Stephen Boyd wrote:
> >
> > Quoting Sergio Paracuellos (2021-03-23 01:13:22)
> > > On Tue, Mar 9, 2021 at 6:22 AM Sergio Paracuellos
> > > wrote:
> > > >
> > > > Changes in v11:
> > > > - Collect R
Hi Stephen,
On Fri, Apr 9, 2021 at 8:17 PM Stephen Boyd wrote:
>
> Quoting Sergio Paracuellos (2021-03-23 01:13:22)
> > On Tue, Mar 9, 2021 at 6:22 AM Sergio Paracuellos
> > wrote:
> > >
> > > Changes in v11:
> > > - Collect Rob's Reviewed-by in bindings documentation patch.
> > > - Fix MAINTA
ntifier: GPL-2.0-only
> +#
> +# MediaTek Mt7621 Clock Driver
> +#
> +menu "Clock driver for Mediatek mt7621 SoC"
> + depends on SOC_MT7621 || COMPILE_TEST
Do we need a menu and a config that says the same thing? Maybe the menu
can be dropped?
> +
> +config CLK_MT7
Enable A7 PLL driver and APCS clock driver on SDX55 platform.
Signed-off-by: Manivannan Sadhasivam
---
arch/arm/configs/qcom_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs/qcom_defconfig
index 0b9da27f923a..02f6185f31a6 100644
b/drivers/clk/hisilicon/Kconfig
index 6a9e93a..5ecc37a 100644
--- a/drivers/clk/hisilicon/Kconfig
+++ b/drivers/clk/hisilicon/Kconfig
@@ -15,6 +15,13 @@ config COMMON_CLK_HI3519
help
Build the clock driver for hi3519.
+config COMMON_CLK_HI3559A
+ bool "Hi3559A Clock D
#x27;memc'. With
>this changes architecture dependent include 'asm/mach-ralink/ralink_regs.h'
>is not needed anymore because we access this two syscons using a phandle
>through kernel's regmap APIs. Explanation of this two areas is in [2].
> - Add new 'mt7621
t;drivers/clk/samsung/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 5325847469e9..1b35ad852721 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -98,6 +98,7 @@ obj-$(CONFIG_COMMON_CLK_NXP) += nxp/
obj-$(CONFIG_MACH_PISTACHIO) += pistachio/
obj
ugh kernel's regmap APIs. Explanation of this two areas is in [2].
- Add new 'mt7621_clk_priv' struct to store there pointers to regmap handlers
to be able to use regmap operations from normal clock api functions. Add
this pointer in 'mt7621_clk' and 'mt7621_clk_
t;drivers/clk/samsung/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 5325847469e9..1b35ad852721 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -98,6 +98,7 @@ obj-$(CONFIG_COMMON_CLK_NXP) += nxp/
obj-$(CONFIG_MACH_PISTACHIO) += pistachio/
obj
e able to use regmap operations from normal clock api functions. Add
this pointer in 'mt7621_clk' and 'mt7621_clk_gate' before register its
related clocks to make things work.
- Add Greg's Acked-by in patches 4 and 5.
- Rebase this series on the top of linux-next ta
t;drivers/clk/samsung/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 5325847469e9..1b35ad852721 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -98,6 +98,7 @@ obj-$(CONFIG_COMMON_CLK_NXP) += nxp/
obj-$(CONFIG_MACH_PISTACHIO) += pistachio/
obj
es. Most
of other drivers just make use of platform operations defined in
'asm/mach-ralink/ralink_regs.h' but this can be avoided declaring this
two nodes to be accesible through syscon. Since these are the only two
needed control interfaces for this clock driver that seems to be the
cor
es. Most
of other drivers just make use of platform operations defined in
'asm/mach-ralink/ralink_regs.h' but this can be avoided declaring this
two nodes to be accesible through syscon. Since these are the only two
needed control interfaces for this clock driver that seems to be the
cor
t;drivers/clk/samsung/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 5325847469e9..1b35ad852721 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -98,6 +98,7 @@ obj-$(CONFIG_COMMON_CLK_NXP) += nxp/
obj-$(CONFIG_MACH_PISTACHIO) += pistachio/
obj
patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Sergio-Paracuellos/MIPS-ralink-add-CPU-clock-detection-and-clock-driver-for-MT7621/20210217-194316
base: https://git.kernel.org/pub/scm/linux/
t;drivers/clk/samsung/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 5325847469e9..1b35ad852721 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -98,6 +98,7 @@ obj-$(CONFIG_COMMON_CLK_NXP) += nxp/
obj-$(CONFIG_MACH_PISTACHIO) += pistachio/
obj
es. Most
of other drivers just make use of platform operations defined in
'asm/mach-ralink/ralink_regs.h' but this can be avoided declaring this
two nodes to be accesible through syscon. Since these are the only two
needed control interfaces for this clock driver that seems to be the
cor
t;drivers/clk/samsung/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 5325847469e9..1b35ad852721 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -98,6 +98,7 @@ obj-$(CONFIG_COMMON_CLK_NXP) += nxp/
obj-$(CONFIG_MACH_PISTACHIO) += pistachio/
obj
es. Most
of other drivers just make use of platform operations defined in
'asm/mach-ralink/ralink_regs.h' but this can be avoided declaring this
two nodes to be accesible through syscon. Since these are the only two
needed control interfaces for this clock driver that seems to be the
cor
Quoting Dinh Nguyen (2021-02-12 06:30:59)
> Add support for Intel's eASIC N5X platform. The clock manager driver for
> the N5X is very similar to the Agilex platform, we can re-use most of
> the Agilex clock driver.
>
> This patch makes the necessary changes for the dri
On 2/10/21 9:05 PM, Stephen Boyd wrote:
Quoting Dinh Nguyen (2021-01-05 11:29:56)
Add support for Intel's eASIC N5X platform. The clock manager driver for
the N5X is very similar to the Agilex platform, we can re-use most of
the Agilex clock driver.
This patch makes the necessary ch
Add support for Intel's eASIC N5X platform. The clock manager driver for
the N5X is very similar to the Agilex platform, we can re-use most of
the Agilex clock driver.
This patch makes the necessary changes for the driver to differentiate
between the Agilex and the N5X platforms.
Signed-o
Quoting Dinh Nguyen (2021-01-05 11:29:56)
> Add support for Intel's eASIC N5X platform. The clock manager driver for
> the N5X is very similar to the Agilex platform, we can re-use most of
> the Agilex clock driver.
>
> This patch makes the necessary changes for the dri
Quoting Vinod Koul (2021-01-26 23:08:11)
> From: Vivek Aknurwar
>
> This adds Global Clock controller (GCC) driver for SM8350 SoC
>
> Signed-off-by: Vivek Aknurwar
> Signed-off-by: Jeevan Shriram
> [vkoul: rebase and tidy up for upstream]
> Signed-off-by: Vinod Koul
> Reviewed-by: Bjorn Ander
From: Vivek Aknurwar
This adds Global Clock controller (GCC) driver for SM8350 SoC
Signed-off-by: Vivek Aknurwar
Signed-off-by: Jeevan Shriram
[vkoul: rebase and tidy up for upstream]
Signed-off-by: Vinod Koul
Reviewed-by: Bjorn Andersson
---
drivers/clk/qcom/Kconfig |8 +
drivers/
From: Gabriel Fernandez
RCC clock and reset controller shared same memory mapping.
As RCC clock driver is now a module, the best way to register clock
and reset controller is to do it in same driver.
Signed-off-by: Gabriel Fernandez
---
drivers/clk/clk-stm32mp1.c | 157
From: Peter Geis
[ Upstream commit f4eccc7fea203cfb35205891eced1ab51836f362 ]
Current implementation defaults the hda clocks to clk_m. This causes hda
to run too slow to operate correctly. Fix this by defaulting to pll_p and
setting the frequency to the correct rate.
This matches upstream t124
From: Peter Geis
[ Upstream commit f4eccc7fea203cfb35205891eced1ab51836f362 ]
Current implementation defaults the hda clocks to clk_m. This causes hda
to run too slow to operate correctly. Fix this by defaulting to pll_p and
setting the frequency to the correct rate.
This matches upstream t124
From: Peter Geis
[ Upstream commit f4eccc7fea203cfb35205891eced1ab51836f362 ]
Current implementation defaults the hda clocks to clk_m. This causes hda
to run too slow to operate correctly. Fix this by defaulting to pll_p and
setting the frequency to the correct rate.
This matches upstream t124
On Sun 17 Jan 22:43 CST 2021, Vinod Koul wrote:
> From: Vivek Aknurwar
>
> This adds Global Clock controller (GCC) driver for SM8350 SoC
>
> Signed-off-by: Vivek Aknurwar
> Signed-off-by: Jeevan Shriram
> [vkoul: rebase and tidy up for upstream]
> Signed-off-by: Vinod Koul
Reviewed-by: Bjor
From: Gabriel Fernandez
RCC clock and reset controller shared same memory mapping.
As RCC clock driver is now a module, the best way to register clock
and reset controller is to do it in same driver.
Signed-off-by: Gabriel Fernandez
---
drivers/clk/clk-stm32mp1.c | 157
From: Peter Geis
[ Upstream commit f4eccc7fea203cfb35205891eced1ab51836f362 ]
Current implementation defaults the hda clocks to clk_m. This causes hda
to run too slow to operate correctly. Fix this by defaulting to pll_p and
setting the frequency to the correct rate.
This matches upstream t124
From: Peter Geis
[ Upstream commit f4eccc7fea203cfb35205891eced1ab51836f362 ]
Current implementation defaults the hda clocks to clk_m. This causes hda
to run too slow to operate correctly. Fix this by defaulting to pll_p and
setting the frequency to the correct rate.
This matches upstream t124
From: Peter Geis
[ Upstream commit f4eccc7fea203cfb35205891eced1ab51836f362 ]
Current implementation defaults the hda clocks to clk_m. This causes hda
to run too slow to operate correctly. Fix this by defaulting to pll_p and
setting the frequency to the correct rate.
This matches upstream t124
Hi Stephen/Mike,
Was wondering if you had a chance to review this patch?
Thanks,
Dinh
On 1/5/21 1:29 PM, Dinh Nguyen wrote:
Add support for Intel's eASIC N5X platform. The clock manager driver for
the N5X is very similar to the Agilex platform, we can re-use most of
the Agilex clock d
From: Vivek Aknurwar
This adds Global Clock controller (GCC) driver for SM8350 SoC
Signed-off-by: Vivek Aknurwar
Signed-off-by: Jeevan Shriram
[vkoul: rebase and tidy up for upstream]
Signed-off-by: Vinod Koul
---
drivers/clk/qcom/Kconfig |8 +
drivers/clk/qcom/Makefile |1 +
o he share code[1] where
> some frequencies and clock parents for the gates are coded from a
> real mediatek private clock plan.
>
> I do really want this to be upstreamed so according to the comments
> in previous attempt[0] from Oleksij Rempel and the frequencies in
> code[1] I h
> diff --git a/drivers/clk/hisilicon/clk-hi3559a.c
> b/drivers/clk/hisilicon/clk-hi3559a.c
> new file mode 100644
> index ..d7693e488006
> --- /dev/null
> +++ b/drivers/clk/hisilicon/clk-hi3559a.c
> @@ -0,0 +1,865 @@
> +// SPDX-License-Identifier: GPL-
On Fri, Jan 08, 2021 at 01:59:12PM +, Peter Geis wrote:
> Current implementation defaults the hda clocks to clk_m. This causes hda
> to run too slow to operate correctly. Fix this by defaulting to pll_p and
> setting the frequency to the correct rate.
>
> This matches upstream t124 and downstr
On 1/8/2021 7:29 PM, Peter Geis wrote:
External email: Use caution opening links or attachments
Current implementation defaults the hda clocks to clk_m. This causes hda
to run too slow to operate correctly. Fix this by defaulting to pll_p and
setting the frequency to the correct rate.
This
Current implementation defaults the hda clocks to clk_m. This causes hda
to run too slow to operate correctly. Fix this by defaulting to pll_p and
setting the frequency to the correct rate.
This matches upstream t124 and downstream t30.
Acked-by: Jon Hunter
Tested-by: Ion Agorria
Signed-off-by:
Add support for Intel's eASIC N5X platform. The clock manager driver for
the N5X is very similar to the Agilex platform, we can re-use most of
the Agilex clock driver.
This patch makes the necessary changes for the driver to differentiate
between the Agilex and the N5X platforms.
Signed-o
From: Vivek Aknurwar
This adds Global Clock controller (GCC) driver for SM8350 SoC
Signed-off-by: Vivek Aknurwar
Signed-off-by: Jeevan Shriram
[vkoul: rebase and tidy up for upstream]
Signed-off-by: Vinod Koul
---
drivers/clk/qcom/Kconfig |8 +
drivers/clk/qcom/Makefile |1 +
On 25/12/2020 01:20, Peter Geis wrote:
> Current implementation defaults the hda clocks to clk_m.
> This causes hda to run too slow to operate correctly.
> Fix this by defaulting to pll_p and setting the frequency to the correct rate.
>
> This matches upstream t124 and downstream t30.
>
> Signe
Current implementation defaults the hda clocks to clk_m.
This causes hda to run too slow to operate correctly.
Fix this by defaulting to pll_p and setting the frequency to the correct rate.
This matches upstream t124 and downstream t30.
Signed-off-by: Peter Geis
Tested-by: Ion Agorria
---
driv
clock parents for the gates are coded from a
real mediatek private clock plan.
I do really want this to be upstreamed so according to the comments
in previous attempt[0] from Oleksij Rempel and the frequencies in
code[1] I have tried to do this
s/clk/samsung/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index dbdc590e7de3..29b957d83c4e 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -101,6 +101,7 @@ obj-$(CONFIG_COMMON_CLK_NXP)+= nxp/
obj-$(CONFIG_MACH_PISTACHIO) += pistachio/
9f13fe7c
> > > > --- /dev/null
> > > > +++ b/drivers/clk/ralink/clk-mt7621.c
> > > > @@ -0,0 +1,435 @@
> > > > +// SPDX-License-Identifier: GPL-2.0
> > > > +/*
> > > > + * Mediatek MT7621 Clock Driver
> > > > + * Au
ig"
> > source "drivers/clk/samsung/Kconfig"
> > diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> > index da8fcf147eb1..6578e167b047 100644
> > --- a/drivers/clk/Makefile
> > +++ b/drivers/clk/Makefile
> > @@ -100,6 +100,7 @@ obj-$(CONFIG_COMMON_CLK_NXP
g"
> source "drivers/clk/renesas/Kconfig"
> source "drivers/clk/rockchip/Kconfig"
> source "drivers/clk/samsung/Kconfig"
> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> index da8fcf147eb1..6578e167b047 100644
> --- a/drivers/clk/Mak
/Kconfig
@@ -15,6 +15,13 @@ config COMMON_CLK_HI3519
help
Build the clock driver for hi3519.
+config COMMON_CLK_HI3559A
+ bool "Hi3559A Clock Driver"
+ depends on ARCH_HISI || COMPILE_TEST
+ default ARCH_HISI
+ help
+ Build the clock
Hi Taniya,
On 13-12-20, 14:00, Taniya Das wrote:
>
>
> On 12/11/2020 12:40 PM, Stephen Boyd wrote:
> > Quoting Vinod Koul (2020-12-10 21:43:49)
> > > On 10-12-20, 12:43, Stephen Boyd wrote:
> > > > > +static struct clk_branch gcc_camera_ahb_clk = {
> > > > > + .halt_reg = 0x26004,
> > > >
On 12/11/2020 12:40 PM, Stephen Boyd wrote:
Quoting Vinod Koul (2020-12-10 21:43:49)
On 10-12-20, 12:43, Stephen Boyd wrote:
+static struct clk_branch gcc_camera_ahb_clk = {
+ .halt_reg = 0x26004,
+ .halt_check = BRANCH_HALT_DELAY,
+ .hwcg_reg = 0x26004,
+ .hwcg_bit =
/Kconfig
@@ -15,6 +15,13 @@ config COMMON_CLK_HI3519
help
Build the clock driver for hi3519.
+config COMMON_CLK_HI3559A
+ bool "Hi3559A Clock Driver"
+ depends on ARCH_HISI || COMPILE_TEST
+ default ARCH_HISI
+ help
+ Build the clock
/Kconfig
@@ -15,6 +15,13 @@ config COMMON_CLK_HI3519
help
Build the clock driver for hi3519.
+config COMMON_CLK_HI3559A
+ bool "Hi3559A Clock Driver"
+ depends on ARCH_HISI || COMPILE_TEST
+ default ARCH_HISI
+ help
+ Build the clock
/Kconfig
@@ -15,6 +15,13 @@ config COMMON_CLK_HI3519
help
Build the clock driver for hi3519.
+config COMMON_CLK_HI3559A
+ bool "Hi3559A Clock Driver"
+ depends on ARCH_HISI || COMPILE_TEST
+ default ARCH_HISI
+ help
+ Build the clock
Quoting Vinod Koul (2020-12-10 21:43:49)
> On 10-12-20, 12:43, Stephen Boyd wrote:
> > > +static struct clk_branch gcc_camera_ahb_clk = {
> > > + .halt_reg = 0x26004,
> > > + .halt_check = BRANCH_HALT_DELAY,
> > > + .hwcg_reg = 0x26004,
> > > + .hwcg_bit = 1,
> > > + .
On 10-12-20, 12:43, Stephen Boyd wrote:
> Quoting Vinod Koul (2020-12-07 22:47:02)
> > +config SM_GCC_8350
> > + tristate "SM8350 Global Clock Controller"
> > + select QCOM_GDSC
> > + help
> > + Support for the global clock controller on SM8350 devices.
> > + Say
Quoting Vinod Koul (2020-12-07 22:47:02)
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index 3a965bd326d5..5015dd9332cd 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -437,6 +437,15 @@ config SM_GCC_8250
> Say Y if you want to use peri
On 09. 12. 20 3:14, quanyang.w...@windriver.com wrote:
> From: Quanyang Wang
>
> The Zynqmp Ultrascale clock controller generates clocks for peripherals
> by default. So enable this clock driver for ZynqMP platforms.
>
> Signed-off-by: Quanyang Wang
> ---
> arch/arm
MIPS: ralink: add clock device providing cpu/ahb/apb clock for mt7621.
> - Move all relevant clock code to 'drivers/clk/ralink/clk-mt7621.c' and
> unify there previous 'mt7621-pll' and 'mt7621-clk' into a unique driver
>and binding 'mt7621-clk
From: Quanyang Wang
The Zynqmp Ultrascale clock controller generates clocks for peripherals
by default. So enable this clock driver for ZynqMP platforms.
Signed-off-by: Quanyang Wang
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs
From: Vivek Aknurwar
This adds Global Clock controller (GCC) driver for SM8350 SoC
Signed-off-by: Vivek Aknurwar
Signed-off-by: Jeevan Shriram
[vkoul: rebase and tidy up for upstream]
Signed-off-by: Vinod Koul
---
drivers/clk/qcom/Kconfig |9 +
drivers/clk/qcom/Makefile |1 +
Hi Taniya,
On 04-12-20, 14:20, Taniya Das wrote:
> On 12/4/2020 10:05 AM, Vinod Koul wrote:
> > On 03-12-20, 18:06, Bjorn Andersson wrote:
> > > On Thu 03 Dec 01:02 CST 2020, Vinod Koul wrote:
> > > > diff --git a/drivers/clk/qcom/gcc-sm8350.c
> > > > b/drivers/clk/qcom/gcc-sm8350.c
> > > [..]
>
Hi Vinod,
On 12/4/2020 10:05 AM, Vinod Koul wrote:
Hi Bjorn,
On 03-12-20, 18:06, Bjorn Andersson wrote:
On Thu 03 Dec 01:02 CST 2020, Vinod Koul wrote:
diff --git a/drivers/clk/qcom/gcc-sm8350.c b/drivers/clk/qcom/gcc-sm8350.c
[..]
+static int gcc_sm8350_probe(struct platform_device *pdev)
Hi Bjorn,
On 03-12-20, 18:06, Bjorn Andersson wrote:
> On Thu 03 Dec 01:02 CST 2020, Vinod Koul wrote:
> > diff --git a/drivers/clk/qcom/gcc-sm8350.c b/drivers/clk/qcom/gcc-sm8350.c
> [..]
> > +static int gcc_sm8350_probe(struct platform_device *pdev)
> > +{
> > + struct regmap *regmap;
> > +
On Thu 03 Dec 01:02 CST 2020, Vinod Koul wrote:
> diff --git a/drivers/clk/qcom/gcc-sm8350.c b/drivers/clk/qcom/gcc-sm8350.c
[..]
> +static int gcc_sm8350_probe(struct platform_device *pdev)
> +{
> + struct regmap *regmap;
> + int ret;
> +
> + regmap = qcom_cc_map(pdev, &gcc_sm8350_desc
From: Vivek Aknurwar
This adds Global Clock controller (GCC) driver for SM8350 SoC
Signed-off-by: Vivek Aknurwar
Signed-off-by: Jeevan Shriram
[vkoul: rebase and tidy up for upstream]
Signed-off-by: Vinod Koul
---
drivers/clk/qcom/Kconfig |9 +
drivers/clk/qcom/Makefile |1 +
e and now make use of 'CLK_OF_DECLARE'
because we need clocks available in 'plat_time_init' before setting up
the timer for the GIC.
- Use new fixed clocks as parents for different gates and deriving from 'xtal'
using frequencies in[1].
- Adapt dts file an
s/clk/samsung/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index da8fcf147eb1..6578e167b047 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -100,6 +100,7 @@ obj-$(CONFIG_COMMON_CLK_NXP)+= nxp/
obj-$(CONFIG_MACH_PISTACHIO) += pistachio/
obj
/Kconfig
@@ -15,6 +15,13 @@ config COMMON_CLK_HI3519
help
Build the clock driver for hi3519.
+config COMMON_CLK_HI3559A
+ bool "Hi3559A Clock Driver"
+ depends on ARCH_HISI || COMPILE_TEST
+ default ARCH_HISI
+ help
+ Build the clock
/Kconfig
@@ -15,6 +15,13 @@ config COMMON_CLK_HI3519
help
Build the clock driver for hi3519.
+config COMMON_CLK_HI3559A
+ bool "Hi3559A Clock Driver"
+ depends on ARCH_HISI || COMPILE_TEST
+ default ARCH_HISI
+ help
+ Build the clock
Hi,
On Thu, Nov 19, 2020 at 10:32 AM Chuanhong Guo wrote:
>
> Hi!
>
> On Fri, Nov 13, 2020 at 11:46 PM Sergio Paracuellos
> wrote:
> > [...]
> > diff --git a/drivers/clk/ralink/Makefile b/drivers/clk/ralink/Makefile
> > new file mode 100644
> > index ..cf6f9216379d
> > --- /dev/null
Hi!
On Fri, Nov 13, 2020 at 11:46 PM Sergio Paracuellos
wrote:
> [...]
> diff --git a/drivers/clk/ralink/Makefile b/drivers/clk/ralink/Makefile
> new file mode 100644
> index ..cf6f9216379d
> --- /dev/null
> +++ b/drivers/clk/ralink/Makefile
Why ralink? The clock design of mt7621 doe
/Kconfig
@@ -15,6 +15,13 @@ config COMMON_CLK_HI3519
help
Build the clock driver for hi3519.
+config COMMON_CLK_HI3559A
+ bool "Hi3559A Clock Driver"
+ depends on ARCH_HISI || COMPILE_TEST
+ default ARCH_HISI
+ help
+ Build the clock
s/clk/samsung/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index da8fcf147eb1..6578e167b047 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -100,6 +100,7 @@ obj-$(CONFIG_COMMON_CLK_NXP)+= nxp/
obj-$(CONFIG_MACH_PISTACHIO) += pistachio/
obj
s/clk/samsung/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index da8fcf147eb1..6578e167b047 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -100,6 +100,7 @@ obj-$(CONFIG_COMMON_CLK_NXP)+= nxp/
obj-$(CONFIG_MACH_PISTACHIO) += pistachio/
obj
/Kconfig b/drivers/clk/hisilicon/Kconfig
index 6a9e93a0bb95..5ecc37aaa118 100644
--- a/drivers/clk/hisilicon/Kconfig
+++ b/drivers/clk/hisilicon/Kconfig
@@ -15,6 +15,13 @@ config COMMON_CLK_HI3519
help
Build the clock driver for hi3519.
+config COMMON_CLK_HI3559A
+ bool
/Kconfig b/drivers/clk/hisilicon/Kconfig
index 6a9e93a0bb95..5ecc37aaa118 100644
--- a/drivers/clk/hisilicon/Kconfig
+++ b/drivers/clk/hisilicon/Kconfig
@@ -15,6 +15,13 @@ config COMMON_CLK_HI3519
help
Build the clock driver for hi3519.
+config COMMON_CLK_HI3559A
+ bool
100-clock.h
>>
>> diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
>> index 6a9e93a0bb95..5ecc37aaa118 100644
>> --- a/drivers/clk/hisilicon/Kconfig
>> +++ b/drivers/clk/hisilicon/Kconfig
>> @@ -15,6 +15,13 @@ config COMMON_CLK_HI3519
>>
rivers/clk/hisilicon/Kconfig
> +++ b/drivers/clk/hisilicon/Kconfig
> @@ -15,6 +15,13 @@ config COMMON_CLK_HI3519
> help
> Build the clock driver for hi3519.
>
> +config COMMON_CLK_HI3559A
> + bool "Hi3559A Clock Driver"
> + depends on ARCH_HIS
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