On 06/28/2007 07:57 PM, Con Kolivas wrote:
> On Friday 29 June 2007 09:33, Siddha, Suresh B wrote:
>> On Fri, Jun 29, 2007 at 09:31:44AM +1000, Con Kolivas wrote:
>>> This is a Q6600 which has cache size of 8 MB. Unless it's reporting each
>>> half's effective L2, I think it should be reporting 819
On Friday 29 June 2007 09:33, Siddha, Suresh B wrote:
> On Fri, Jun 29, 2007 at 09:31:44AM +1000, Con Kolivas wrote:
> > This is a Q6600 which has cache size of 8 MB. Unless it's reporting each
> > half's effective L2, I think it should be reporting 8192 instead of 4096.
>
> There are two L2's, eac
On Fri, Jun 29, 2007 at 09:31:44AM +1000, Con Kolivas wrote:
> This is a Q6600 which has cache size of 8 MB. Unless it's reporting each
> half's effective L2, I think it should be reporting 8192 instead of 4096.
>
Each pair of cores appears to get 4MB of L2, according to the product
brief PDF on
On Fri, Jun 29, 2007 at 09:31:44AM +1000, Con Kolivas wrote:
> This is a Q6600 which has cache size of 8 MB. Unless it's reporting each
> half's effective L2, I think it should be reporting 8192 instead of 4096.
There are two L2's, each of 4MB. Each L2 shared by two cores.
thanks,
suresh
>
> O
This is a Q6600 which has cache size of 8 MB. Unless it's reporting each
half's effective L2, I think it should be reporting 8192 instead of 4096.
On 2.6.22-rc6:
cat /proc/cpuinfo
processor : 0
vendor_id : GenuineIntel
cpu family : 6
model : 15
model name : Intel(
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