On 12/10/2013 10:53 PM, Arjan van de Ven wrote:
> On 12/9/2013 10:08 PM, Alex Shi wrote:
>> And for monitor/mwait idle method, seems deep c-state cpu need to keep a
>> eye on memory bus. So seems the memory controller in cpu package is
>> impossible to get into sleep, right?
> not the memory bus
>
On 12/9/2013 10:08 PM, Alex Shi wrote:
And for monitor/mwait idle method, seems deep c-state cpu need to keep a
eye on memory bus. So seems the memory controller in cpu package is
impossible to get into sleep, right?
not the memory bus
the cache coherency logic ;-)
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On 12/10/2013 03:27 PM, Daniel Lezcano wrote:
>
>> And does the wake up pass via GIC to CPU? If so, does the GIC need
>> keep awake when all cpu idle? If not, how the firmware give the
>> interrupt to CPU? And I am wondering if the deep idle cpu voltage get
>> to near 0. How the cpu get the interr
On 12/10/2013 09:07 AM, anish singh wrote:
On Mon, Dec 9, 2013 at 11:27 PM, Daniel Lezcano
wrote:
On 12/10/2013 07:33 AM, Alex Shi wrote:
On 12/09/2013 10:17 PM, Daniel Lezcano wrote:
Concerning the wake up of the cpu: the cpu disabled the irq and
goes to sleep, it is up to the firmware to
On Mon, Dec 9, 2013 at 11:27 PM, Daniel Lezcano
wrote:
> On 12/10/2013 07:33 AM, Alex Shi wrote:
>>
>> On 12/09/2013 10:17 PM, Daniel Lezcano wrote:
>>>
>>>
>>> Concerning the wake up of the cpu: the cpu disabled the irq and
>>> goes to sleep, it is up to the firmware to wake up the cpu when an
>>
On 12/10/2013 07:33 AM, Alex Shi wrote:
On 12/09/2013 10:17 PM, Daniel Lezcano wrote:
Concerning the wake up of the cpu: the cpu disabled the irq and
goes to sleep, it is up to the firmware to wake up the cpu when an
interrupt occurs. It will exits its sleep state, call
clock_events_notify(EXIT
On 12/09/2013 10:17 PM, Daniel Lezcano wrote:
>
> Concerning the wake up of the cpu: the cpu disabled the irq and goes to
> sleep, it is up to the firmware to wake up the cpu when an interrupt
> occurs. It will exits its sleep state, call clock_events_notify(EXIT),
> by this way re-switching to th
On 12/09/2013 11:26 PM, Preeti U Murthy wrote:
>> > If the cpu stopped the interrupt during deep c-state and without
>> > monitor/mwait support, which kind of ipi can wake the cpu? I mean like a
>> > x86 cpu, APIC stopped in c3 mode, but actually ipi send via apic bus. So
>> > I don't know which ip
Hi Alex,
On 12/09/2013 07:10 PM, Alex Shi wrote:
>
> Sorry for a idiot of cpuidle.
>
> I just find few cpu set TIMER_STOP on cpuidle, like omap4 and big.Little
> driver. Does that mean other ARM cpu or x86 cpu can get the timer
> interrupt in cpuidle?
There could be. Its only in some architectu
On 12/09/2013 02:40 PM, Alex Shi wrote:
Sorry for a idiot of cpuidle.
I just find few cpu set TIMER_STOP on cpuidle, like omap4 and big.Little
driver. Does that mean other ARM cpu or x86 cpu can get the timer
interrupt in cpuidle?
If the timer stopped during cpuidle, does that means at least o
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