On Thu, 12 Jul 2007, Songmao Tian wrote:
> 8259 problem seems to be done with the attached patch, IDE hung seems to be
> the dma setting problem.
>
> Thanks all for your advise, comments. I have learned a lot. now I continue to
> trace down the IDE problem.
I would still recommend you to inves
8259 problem seems to be done with the attached patch, IDE hung seems
to be the dma setting problem.
Thanks all for your advise, comments. I have learned a lot. now I
continue to trace down the IDE problem.
Mao
Maciej W. Rozycki wrote:
On Wed, 11 Jul 2007, Songmao Tian wrote:
Huh? Ha
On Wed, 11 Jul 2007, Maciej W. Rozycki wrote:
> > > You can still dispatch interrupts manually by examining the IRR register,
> > > but having a way to ask the 8259A's prioritiser would be nice. Although
> > > given such a lethal erratum you report I would not count on the
> > > prioritiser
> >
Hi,
> > does it return if you write 0xc to the address 0x20 in the I/O port space
> > and then read back from that location? You should complain to the
> > manufacturer -- they may be able to fix the problem in a later revision.
>
>Haha, here's an excerpt form CS5535 spec. update:
>
> 96. P
On Wed, 11 Jul 2007, Songmao Tian wrote:
> > Huh? Have you managed to find an 8259A clone *that* broken? So what does
> > it return if you write 0xc to the address 0x20 in the I/O port space and
> > then read back from that location? You should complain to the
> >
>
> It's the value of IRR
Hello.
Maciej W. Rozycki wrote:
"Control Logic
The INT output goes directly to the CPU interrupt input.
When an INT signal is activated, the CPU responds with an
Interrupt Acknowledge access that is translated to two
pulses on the INTA input of the PIC. At the first INTA pulse,
the highest prio
Songmao Tian wrote:
Before I post the mail, I think you will reply, and haha you did:),
Thanks that.
Maciej W. Rozycki wrote:
On Wed, 11 Jul 2007, Songmao Tian wrote:
"Control Logic
The INT output goes directly to the CPU interrupt input.
When an INT signal is activated, the CPU responds w
Sergei Shtylyov wrote:
Hello, I wrote:
it's a problem that my northbridge didn't implement that!
Fortunately we use a fpga as a northbridge.
Wait, CS5536 is a nortbridge itself!
Apparently, it's only a south bridge. I must've mixed it with Geode
itself.
WBR, Sergei
that's fine
Hello, I wrote:
it's a problem that my northbridge didn't implement that! Fortunately
we use a fpga as a northbridge.
Wait, CS5536 is a nortbridge itself!
Apparently, it's only a south bridge. I must've mixed it with Geode itself.
WBR, Sergei
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Songmao Tian wrote:
Hi,
I am trying to use a mips cpu the cs5536. I have some problem with
the 8259 of cs5536. The databook said,
Which databook?
"Control Logic
The INT output goes directly to the CPU interrupt input.
When an INT signal is activated, the CPU responds with an
Interr
Before I post the mail, I think you will reply, and haha you did:),
Thanks that.
Maciej W. Rozycki wrote:
On Wed, 11 Jul 2007, Songmao Tian wrote:
"Control Logic
The INT output goes directly to the CPU interrupt input.
When an INT signal is activated, the CPU responds with an
Interrupt Ack
On Wed, 11 Jul 2007, Songmao Tian wrote:
> "Control Logic
> The INT output goes directly to the CPU interrupt input.
> When an INT signal is activated, the CPU responds with an
> Interrupt Acknowledge access that is translated to two
> pulses on the INTA input of the PIC. At the first INTA pulse,
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