> Intel486???, Pentium??, or P6 family processors. The P6 family processors
> provide bus control signals that permit external memory subsystems to
> make split accesses atomic; however, nonaligned data accesses will
Normally in standard SMP systems between CPUs they are atomic AFAIK
(modulo bugs
> > > Are misaligned/cross-cache-line updates atomic?
> >
> > In theory yes, in practice there can be errata of course.
Afaik the theory is "Platform specific; most x86 will be in practice";
it's up to the system vendor and chipset vendor.
The practice is "mixed ball, slow as h*ck anyway, jus
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