Hi Peter,
On Wed, 2017-01-25 at 12:34 -0800, H. Peter Anvin wrote:
> On 01/25/17 12:23, Ricardo Neri wrote:
> > * SMSW returns the value with which the CR0 register is programmed in
> >head_32/64.S at boot time. This is, the following bits are enabed:
> >CR0.0 for Protection Enable, CR.1 f
On 01/25/17 12:23, Ricardo Neri wrote:
> * SMSW returns the value with which the CR0 register is programmed in
>head_32/64.S at boot time. This is, the following bits are enabed:
>CR0.0 for Protection Enable, CR.1 for Monitor Coprocessor, CR.4 for
>Extension Type, which will always be
2 matches
Mail list logo
