Re: [patch] Pad irq_desc to internode cacheline size

2007-04-09 Thread Eric W. Biederman
Ravikiran G Thirumalai <[EMAIL PROTECTED]> writes: > !!! No. internode aligned is 4k only if CONFIG_X86_VSMP is chosen. The > internode line size defaults to SMP_CACHE_BYTES for all other machine types. > Please note that an INTERNODE_CACHE_SHIFT of 12 is defined under > #ifdef CONFIG_X86_VSMP i

Re: [patch] Pad irq_desc to internode cacheline size

2007-04-09 Thread Ravikiran G Thirumalai
On Mon, Apr 09, 2007 at 03:47:52PM -0600, Eric W. Biederman wrote: > Andrew Morton <[EMAIL PROTECTED]> writes: > > > This will consume nearly 4k per irq won't it? What is the upper bound > > here, across all configs and all hardware? > > > > Is VSMP the only arch which has cacheline_internode

Re: [patch] Pad irq_desc to internode cacheline size

2007-04-09 Thread Eric W. Biederman
Andrew Morton <[EMAIL PROTECTED]> writes: > This will consume nearly 4k per irq won't it? What is the upper bound > here, across all configs and all hardware? > > Is VSMP the only arch which has cacheline_internodealigned_in_smp > larger than cacheline_aligned_in_smp? Ugh. We set interno

Re: [patch] Pad irq_desc to internode cacheline size

2007-04-09 Thread Andrew Morton
On Mon, 9 Apr 2007 12:56:27 -0700 Ravikiran G Thirumalai <[EMAIL PROTECTED]> wrote: > We noticed a drop in n/w performance due to the irq_desc being cacheline > aligned rather than internode aligned. We see 50% of expected performance > when two e1000 nics local to two different nodes have consec