Re: [RFC 1/2] powerpc/32: Unset MSR RI in exception epilogs

2016-12-14 Thread Peter Zijlstra
On Tue, Dec 13, 2016 at 04:54:30PM -0600, Segher Boessenkool wrote: > On Tue, Dec 13, 2016 at 09:39:55PM +0100, christophe leroy wrote: > > Le 13/12/2016 à 20:15, Segher Boessenkool a écrit : > > >On Tue, Dec 13, 2016 at 07:19:41PM +0100, Christophe Leroy wrote: > > >>At exception prologs, once SRR

Re: [RFC 1/2] powerpc/32: Unset MSR RI in exception epilogs

2016-12-13 Thread Segher Boessenkool
On Tue, Dec 13, 2016 at 09:39:55PM +0100, christophe leroy wrote: > Le 13/12/2016 à 20:15, Segher Boessenkool a écrit : > >On Tue, Dec 13, 2016 at 07:19:41PM +0100, Christophe Leroy wrote: > >>At exception prologs, once SRR0 and SRR1 have been saved, MSR RI is > >>set to mark the interrupt as recov

Re: [RFC 1/2] powerpc/32: Unset MSR RI in exception epilogs

2016-12-13 Thread christophe leroy
Le 13/12/2016 à 20:15, Segher Boessenkool a écrit : On Tue, Dec 13, 2016 at 07:19:41PM +0100, Christophe Leroy wrote: At exception prologs, once SRR0 and SRR1 have been saved, MSR RI is set to mark the interrupt as recoverable. MSR RI has to be unset before writing into SRR0 and SRR1 at except

Re: [RFC 1/2] powerpc/32: Unset MSR RI in exception epilogs

2016-12-13 Thread Segher Boessenkool
On Tue, Dec 13, 2016 at 07:19:41PM +0100, Christophe Leroy wrote: > At exception prologs, once SRR0 and SRR1 have been saved, MSR RI is > set to mark the interrupt as recoverable. > > MSR RI has to be unset before writing into SRR0 and SRR1 at exception > epilogs. Why? What goes wrong without th