Re: [PATCH v8 1/3] clk: qcom: Add A53 PLL support

2017-06-27 Thread Georgi Djakov
On 06/27/2017 12:48 PM, Riku Voipio wrote: > On 26 June 2017 at 22:40, Rob Herring wrote: >> On Fri, Jun 23, 2017 at 07:15:31PM +0300, Georgi Djakov wrote: >>> The CPUs on Qualcomm MSM8916-based platforms are clocked by two PLLs, >>> a primary (A53) CPU PLL and a secondary fixed-rate GPLL0. These

Re: [PATCH v8 1/3] clk: qcom: Add A53 PLL support

2017-06-27 Thread Riku Voipio
On 26 June 2017 at 22:40, Rob Herring wrote: > On Fri, Jun 23, 2017 at 07:15:31PM +0300, Georgi Djakov wrote: >> The CPUs on Qualcomm MSM8916-based platforms are clocked by two PLLs, >> a primary (A53) CPU PLL and a secondary fixed-rate GPLL0. These sources >> are connected to a mux and half-integ

Re: [PATCH v8 1/3] clk: qcom: Add A53 PLL support

2017-06-26 Thread Rob Herring
On Fri, Jun 23, 2017 at 07:15:31PM +0300, Georgi Djakov wrote: > The CPUs on Qualcomm MSM8916-based platforms are clocked by two PLLs, > a primary (A53) CPU PLL and a secondary fixed-rate GPLL0. These sources > are connected to a mux and half-integer divider, which is feeding the > CPU cores. > >