> For repeated start (Sr) scenario, the STOP bit will not be set. For
> dummy write scenario (writing EEPROM address from I2C EEPROM slave),
> the STOP bit should not be set. But, for normal I2C write, the STOP
> bit should be set. We provide control to user to control when to
> STOP/NAK to handle
Hi,
Thanks for reviewing the code.
> > +/*
> > + * It exposes sysfs entries under the i2c adapter for getting the i2c
> > +transfer
> > + * status, reset i2c read/write module, get/set nak and stop bits.
> > + */
>
> Yes, I see that. Yet, I don't know why they are needed? The driver should
> know
Hi,
thanks for this submission. Looks like an interesting device. However,
some very high level questions first:
> +/*
> + * It exposes sysfs entries under the i2c adapter for getting the i2c
> transfer
> + * status, reset i2c read/write module, get/set nak and stop bits.
> + */
Yes, I see that
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