Re: [PATCH v4 13/13] openrisc: add tick timer multi-core sync logic

2017-11-01 Thread Stafford Horne
On Wed, Nov 01, 2017 at 09:26:43AM +, Matt Redfearn wrote: > > > On 01/11/17 00:34, Stafford Horne wrote: > > On Wed, Nov 01, 2017 at 08:17:59AM +0900, Stafford Horne wrote: > > > On Tue, Oct 31, 2017 at 02:06:21PM +, Matt Redfearn wrote: > > > > Hi, > > > > > > > > > > > > On 29/10/17

Re: [PATCH v4 13/13] openrisc: add tick timer multi-core sync logic

2017-11-01 Thread Matt Redfearn
On 01/11/17 00:34, Stafford Horne wrote: On Wed, Nov 01, 2017 at 08:17:59AM +0900, Stafford Horne wrote: On Tue, Oct 31, 2017 at 02:06:21PM +, Matt Redfearn wrote: Hi, On 29/10/17 23:11, Stafford Horne wrote: In case timers are not in sync when cpus start (i.e. hot plug / offset resets

Re: [PATCH v4 13/13] openrisc: add tick timer multi-core sync logic

2017-10-31 Thread Stafford Horne
On Wed, Nov 01, 2017 at 08:17:59AM +0900, Stafford Horne wrote: > On Tue, Oct 31, 2017 at 02:06:21PM +, Matt Redfearn wrote: > > Hi, > > > > > > On 29/10/17 23:11, Stafford Horne wrote: > > > In case timers are not in sync when cpus start (i.e. hot plug / offset > > > resets) we need to synch

Re: [PATCH v4 13/13] openrisc: add tick timer multi-core sync logic

2017-10-31 Thread Stafford Horne
On Tue, Oct 31, 2017 at 02:06:21PM +, Matt Redfearn wrote: > Hi, > > > On 29/10/17 23:11, Stafford Horne wrote: > > In case timers are not in sync when cpus start (i.e. hot plug / offset > > resets) we need to synchronize the secondary cpus internal timer with > > the main cpu. This is neede

Re: [PATCH v4 13/13] openrisc: add tick timer multi-core sync logic

2017-10-31 Thread Matt Redfearn
Hi, On 29/10/17 23:11, Stafford Horne wrote: In case timers are not in sync when cpus start (i.e. hot plug / offset resets) we need to synchronize the secondary cpus internal timer with the main cpu. This is needed as in OpenRISC SMP there is only one clocksource registered which reads from th