On 23/05/17 21:04, Russell King - ARM Linux wrote:
> On Mon, May 15, 2017 at 09:52:58AM +0100, Vladimir Murzin wrote:
>> Ping again...
>
> Apart from the one comment, the ARM bits look fine to me - but I'm
> not saying anything about the lib/dma-noop.c or the drivers/base
> changes.
>
> What's th
On Mon, May 15, 2017 at 09:52:58AM +0100, Vladimir Murzin wrote:
> Ping again...
Apart from the one comment, the ARM bits look fine to me - but I'm
not saying anything about the lib/dma-noop.c or the drivers/base
changes.
What's the dependency between the ARM bits and those bits?
> On 02/05/17 0
Ping again...
On 02/05/17 09:32, Vladimir Murzin wrote:
> Gentle ping!
>
> On 24/04/17 11:16, Vladimir Murzin wrote:
>> It seem that addition of cache support for M-class CPUs uncovered
>> latent bug in DMA usage. NOMMU memory model has been treated as being
>> always consistent; however, for R/M
Gentle ping!
On 24/04/17 11:16, Vladimir Murzin wrote:
> It seem that addition of cache support for M-class CPUs uncovered
> latent bug in DMA usage. NOMMU memory model has been treated as being
> always consistent; however, for R/M CPU classes memory can be covered
> by MPU which in turn might co
4 matches
Mail list logo