nal Message-
> From: jonghwa3@samsung.com [mailto:jonghwa3....@samsung.com]
> Sent: Wednesday, November 21, 2012 1:02 PM
> To: Kyungmin Park
> Cc: Jonghwan Choi; jonghwa3.lee; open list; Amit Daniel Kachhap; Zhang Rui;
> Sachin Kamat
> Subject: Re: [PATCH v3 2/2] therma: exyno
el3_en, but I recommend you to support 3rd trigger level in
> exynos4210 either.
Hi Choi/Lee,
It is fine to enable 4th interrupt level in exynos4210 like exynos5
but the zone will be 3 only. I guess the other parts of code should
take care of this.
Choi,
Please change just the platform data
OC's type is. So, with
my former suggestion,
it can use 3rd thermal trigger level in both SOC group. And it will activate as
THERMAL TRIP in
exynos4x12,5250 and as just 3rd Trigger levels in exynos4210. I do not just
emphasize the use of
Trigger_level3_en, but I recommend you to support 3rd trigge
Hi,
On 2012년 11월 20일 10:40, Kyungmin Park wrote:
> On 11/20/12, Jonghwan Choi wrote:
>> TMU urgently sends active-high signal (thermal trip) to PMU,
>> and thermal tripping by hardware logic i.e PMU is performed.
>> Thermal tripping means that PMU cut off the whole power of SoC
>> by controlling e
On 11/20/12, Jonghwan Choi wrote:
> TMU urgently sends active-high signal (thermal trip) to PMU,
> and thermal tripping by hardware logic i.e PMU is performed.
> Thermal tripping means that PMU cut off the whole power of SoC
> by controlling external voltage regulator.
>
> Signed-off-by: Jonghwan
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