Hei hei,
Am Donnerstag, 29. März 2018, 10:01:26 CEST schrieb Alexander Dahl:
> This is the result:
>
> INTNAME RATE MAX
> 17 [vel timer@fffa] 1837 Ints/s (max: 1912)
> 26 [ vel eth0] 3 Ints/s (max:11)
Above was with v4.16-rc7+
On 29/03/2018 at 14:07:34 +0200, Daniel Lezcano wrote:
> On 29/03/2018 13:42, Alexandre Belloni wrote:
> > On 29/03/2018 at 13:31:18 +0200, Alexander Dahl wrote:
> >> Pretty sure. I rebuilt the whole BSP and added another line to the kernel
> >> source to see if the tree I applied the patches to,
On 29/03/2018 13:42, Alexandre Belloni wrote:
> On 29/03/2018 at 13:31:18 +0200, Alexander Dahl wrote:
>> Pretty sure. I rebuilt the whole BSP and added another line to the kernel
>> source to see if the tree I applied the patches to, was actually built:
>>
>>
>> diff --git a/drivers/clocksource/t
On 29/03/2018 at 13:31:18 +0200, Alexander Dahl wrote:
> Pretty sure. I rebuilt the whole BSP and added another line to the kernel
> source to see if the tree I applied the patches to, was actually built:
>
>
> diff --git a/drivers/clocksource/timer-atmel-tcb.c
> b/drivers/clocksource/timer-atm
Hello Alexandre,
Am Donnerstag, 29. März 2018, 12:45:42 CEST schrieb Alexandre Belloni:
> > This is the result:
> >
> > INTNAME RATE MAX
> >
> > 17 [vel timer@fffa] 1837 Ints/s (max: 1912)
> > 26 [ vel eth0] 3 Ints/s (max:11)
On 29/03/2018 at 10:01:26 +0200, Alexander Dahl wrote:
> Hei hei,
>
> Am Mittwoch, 28. März 2018, 17:50:33 CEST schrieb Alexandre Belloni:
> > On 28/03/2018 at 17:31:35 +0200, Alexandre Belloni wrote:
> > > > Do you have an explanation of why the rate is much higher ?
> > >
> > > The core is givi
Hei hei,
Am Mittwoch, 28. März 2018, 17:50:33 CEST schrieb Alexandre Belloni:
> On 28/03/2018 at 17:31:35 +0200, Alexandre Belloni wrote:
> > > Do you have an explanation of why the rate is much higher ?
> >
> > The core is giving deltas of 31 clocks instead of much more than that, I
> > guess I
On 28/03/2018 at 17:31:35 +0200, Alexandre Belloni wrote:
> > Do you have an explanation of why the rate is much higher ?
> >
>
> The core is giving deltas of 31 clocks instead of much more than that, I
> guess I messed up the initialization somewhere.
>
I did mess up.
Alexander, can you test
On 28/03/2018 at 16:36:34 +0200, Daniel Lezcano wrote:
> On 28/03/2018 16:16, Alexandre Belloni wrote:
> > On 28/03/2018 at 15:03:11 +0200, Daniel Lezcano wrote:
> >> On 28/03/2018 12:29, Alexander Dahl wrote:
> >>> Hello Daniel,
> >>>
> >>> Am Dienstag, 27. März 2018, 13:30:22 CEST schrieb Daniel
On 28/03/2018 16:16, Alexandre Belloni wrote:
> On 28/03/2018 at 15:03:11 +0200, Daniel Lezcano wrote:
>> On 28/03/2018 12:29, Alexander Dahl wrote:
>>> Hello Daniel,
>>>
>>> Am Dienstag, 27. März 2018, 13:30:22 CEST schrieb Daniel Lezcano:
Can you can give a rough amount for the irq rate on t
On 28/03/2018 at 15:03:11 +0200, Daniel Lezcano wrote:
> On 28/03/2018 12:29, Alexander Dahl wrote:
> > Hello Daniel,
> >
> > Am Dienstag, 27. März 2018, 13:30:22 CEST schrieb Daniel Lezcano:
> >> Can you can give a rough amount for the irq rate on the timer ?
> >
> > I used itop [1] now to get a
On 28/03/2018 12:29, Alexander Dahl wrote:
> Hello Daniel,
>
> Am Dienstag, 27. März 2018, 13:30:22 CEST schrieb Daniel Lezcano:
>> Can you can give a rough amount for the irq rate on the timer ?
>
> I used itop [1] now to get a rough estimate. First with kernel v4.14.29-rt25
> (fully preempt RT
Hello Daniel,
Am Dienstag, 27. März 2018, 13:30:22 CEST schrieb Daniel Lezcano:
> Can you can give a rough amount for the irq rate on the timer ?
I used itop [1] now to get a rough estimate. First with kernel v4.14.29-rt25
(fully preempt RT):
INTNAME RATE MA
On 27/03/2018 12:41, Alexander Dahl wrote:
> Hello Alexandre,
>
> Am Freitag, 23. Februar 2018, 18:15:52 CEST schrieb Alexandre Belloni:
>> - using the PIT doesn't work well with preempt-rt because its interrupt is
>>shared (in particular with the UART and their interrupt flags are
>>inco
Hello Alexandre,
Am Freitag, 23. Februar 2018, 18:15:52 CEST schrieb Alexandre Belloni:
> - using the PIT doesn't work well with preempt-rt because its interrupt is
>shared (in particular with the UART and their interrupt flags are
>incompatible)
This is actually quite annoying when usin
Hi Daniel,
I'd really like to get this in the kernel soon as we have platform that
still can't boot with a mainline kernel because they don't have a PIT.
On 23/02/2018 at 18:15:52 +0100, Alexandre Belloni wrote:
> Hi,
>
> This series gets back on the TCB drivers rework. It introduces a new drive
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