On Thu, Oct 10, 2019 at 6:35 AM Tanwar, Rahul
wrote:
> My understanding is
> that GPIO_GENERIC can support a max of 64 consecutive bits representing
> GPIO lines.
Correct, it also demand that all GPIOs are accessed in a single
register of 8, 16, 32 or 64 bits.
> We have more than 100 GPIO's and
Hi Linus,
Thanks for taking time out to review.
On 5/10/2019 4:28 AM, Linus Walleij wrote:
>> +config PINCTRL_EQUILIBRIUM
>> + tristate "Generic pinctrl and GPIO driver for Intel Lightning
>> Mountain SoC"
>> + select PINMUX
>> + select PINCONF
>> + select GPIOLIB
>> +
Hi Rahul,
this is an interesting patch!
Let's dive in and fix the things not already pointed out in review.
It will need some work but I am sure you can get there.
On Thu, Sep 12, 2019 at 9:59 AM Rahul Tanwar
wrote:
> Intel Lightning Mountain SoC has a pinmux controller & GPIO controller IP
>
Hi Andy,
Thanks for your comments. I agree & will address all your review concerns in
v2 except below mentioned points where i need more clarification.
On 12/9/2019 10:30 PM, Andy Shevchenko wrote:
>> +static const struct pin_config pin_cfg_type[] = {
>> +{"intel,pullup",PIN
On Thu, Sep 12, 2019 at 03:59:10PM +0800, Rahul Tanwar wrote:
> Intel Lightning Mountain SoC has a pinmux controller & GPIO controller IP
> which controls pin multiplexing & configuration including GPIO functions
> selection & GPIO attributes configuration. Add GPIO & pin control framework
> based
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