Re: [PATCH bpf-next] bpf: arm64: Redefine MOV consistent with arch insn

2021-03-31 Thread Jianlin Lv
On Wed, Mar 31, 2021 at 5:28 PM Will Deacon wrote: > > On Wed, Mar 31, 2021 at 05:22:18PM +0800, Jianlin Lv wrote: > > On Tue, Mar 30, 2021 at 5:31 PM Will Deacon wrote: > > > > > > On Tue, Mar 30, 2021 at 03:42:35PM +0800, Jianlin Lv wrote: > > > > A64_MOV is currently mapped to Add Instruction.

Re: [PATCH bpf-next] bpf: arm64: Redefine MOV consistent with arch insn

2021-03-31 Thread Will Deacon
On Wed, Mar 31, 2021 at 05:22:18PM +0800, Jianlin Lv wrote: > On Tue, Mar 30, 2021 at 5:31 PM Will Deacon wrote: > > > > On Tue, Mar 30, 2021 at 03:42:35PM +0800, Jianlin Lv wrote: > > > A64_MOV is currently mapped to Add Instruction. Architecturally MOV > > > (register) is an alias of ORR (shifte

Re: [PATCH bpf-next] bpf: arm64: Redefine MOV consistent with arch insn

2021-03-31 Thread Jianlin Lv
On Tue, Mar 30, 2021 at 5:31 PM Will Deacon wrote: > > On Tue, Mar 30, 2021 at 03:42:35PM +0800, Jianlin Lv wrote: > > A64_MOV is currently mapped to Add Instruction. Architecturally MOV > > (register) is an alias of ORR (shifted register) and MOV (to or from SP) > > is an alias of ADD (immediate)

Re: [PATCH bpf-next] bpf: arm64: Redefine MOV consistent with arch insn

2021-03-30 Thread Will Deacon
On Tue, Mar 30, 2021 at 03:42:35PM +0800, Jianlin Lv wrote: > A64_MOV is currently mapped to Add Instruction. Architecturally MOV > (register) is an alias of ORR (shifted register) and MOV (to or from SP) > is an alias of ADD (immediate). > This patch redefines A64_MOV and uses existing functionali