Re: [PATCH V3 2/2] PCI: dwc: Add support to configure for ECRC

2020-11-04 Thread Vidya Sagar
On 11/4/2020 9:52 PM, Bjorn Helgaas wrote: External email: Use caution opening links or attachments On Wed, Nov 04, 2020 at 05:13:07PM +0530, Vidya Sagar wrote: On 11/4/2020 2:37 AM, Bjorn Helgaas wrote: On Tue, Nov 03, 2020 at 08:57:01AM +0530, Vidya Sagar wrote: On 11/3/2020 4:32 AM, Bj

Re: [PATCH V3 2/2] PCI: dwc: Add support to configure for ECRC

2020-11-04 Thread Bjorn Helgaas
On Wed, Nov 04, 2020 at 05:13:07PM +0530, Vidya Sagar wrote: > On 11/4/2020 2:37 AM, Bjorn Helgaas wrote: > > On Tue, Nov 03, 2020 at 08:57:01AM +0530, Vidya Sagar wrote: > > > On 11/3/2020 4:32 AM, Bjorn Helgaas wrote: > > > > On Thu, Oct 29, 2020 at 11:09:59AM +0530, Vidya Sagar wrote: > > > > >

Re: [PATCH V3 2/2] PCI: dwc: Add support to configure for ECRC

2020-11-04 Thread Vidya Sagar
On 11/4/2020 2:37 AM, Bjorn Helgaas wrote: External email: Use caution opening links or attachments On Tue, Nov 03, 2020 at 08:57:01AM +0530, Vidya Sagar wrote: On 11/3/2020 4:32 AM, Bjorn Helgaas wrote: On Thu, Oct 29, 2020 at 11:09:59AM +0530, Vidya Sagar wrote: DesignWare core has a TL

Re: [PATCH V3 2/2] PCI: dwc: Add support to configure for ECRC

2020-11-03 Thread Bjorn Helgaas
On Tue, Nov 03, 2020 at 08:57:01AM +0530, Vidya Sagar wrote: > On 11/3/2020 4:32 AM, Bjorn Helgaas wrote: > > On Thu, Oct 29, 2020 at 11:09:59AM +0530, Vidya Sagar wrote: > > > DesignWare core has a TLP digest (TD) override bit in one of the control > > > registers of ATU. This bit also needs to be

Re: [PATCH V3 2/2] PCI: dwc: Add support to configure for ECRC

2020-11-03 Thread Rob Herring
On Mon, Nov 2, 2020 at 4:38 PM Gustavo Pimentel wrote: > > On Mon, Nov 2, 2020 at 21:16:52, Rob Herring wrote: > > > On Mon, Nov 2, 2020 at 9:12 AM Gustavo Pimentel > > wrote: > > > > > > On Mon, Nov 2, 2020 at 14:27:9, Vidya Sagar wrote: > > > > > > > > > > > > > > > On 11/2/2020 7:45 PM, Rob

Re: [PATCH V3 2/2] PCI: dwc: Add support to configure for ECRC

2020-11-02 Thread Vidya Sagar
On 11/3/2020 4:32 AM, Bjorn Helgaas wrote: External email: Use caution opening links or attachments On Thu, Oct 29, 2020 at 11:09:59AM +0530, Vidya Sagar wrote: DesignWare core has a TLP digest (TD) override bit in one of the control registers of ATU. This bit also needs to be programmed fo

Re: [PATCH V3 2/2] PCI: dwc: Add support to configure for ECRC

2020-11-02 Thread Bjorn Helgaas
On Thu, Oct 29, 2020 at 11:09:59AM +0530, Vidya Sagar wrote: > DesignWare core has a TLP digest (TD) override bit in one of the control > registers of ATU. This bit also needs to be programmed for proper ECRC > functionality. This is currently identified as an issue with DesignWare > IP version 4.9

RE: [PATCH V3 2/2] PCI: dwc: Add support to configure for ECRC

2020-11-02 Thread Gustavo Pimentel
On Mon, Nov 2, 2020 at 21:16:52, Rob Herring wrote: > On Mon, Nov 2, 2020 at 9:12 AM Gustavo Pimentel > wrote: > > > > On Mon, Nov 2, 2020 at 14:27:9, Vidya Sagar wrote: > > > > > > > > > > > On 11/2/2020 7:45 PM, Rob Herring wrote: > > > > External email: Use caution opening links or attachmen

Re: [PATCH V3 2/2] PCI: dwc: Add support to configure for ECRC

2020-11-02 Thread Rob Herring
On Mon, Nov 2, 2020 at 9:12 AM Gustavo Pimentel wrote: > > On Mon, Nov 2, 2020 at 14:27:9, Vidya Sagar wrote: > > > > > > > On 11/2/2020 7:45 PM, Rob Herring wrote: > > > External email: Use caution opening links or attachments > > > > > > > > > On Thu, Oct 29, 2020 at 12:40 AM Vidya Sagar wrote

RE: [PATCH V3 2/2] PCI: dwc: Add support to configure for ECRC

2020-11-02 Thread Gustavo Pimentel
On Mon, Nov 2, 2020 at 14:27:9, Vidya Sagar wrote: > > > On 11/2/2020 7:45 PM, Rob Herring wrote: > > External email: Use caution opening links or attachments > > > > > > On Thu, Oct 29, 2020 at 12:40 AM Vidya Sagar wrote: > >> > >> DesignWare core has a TLP digest (TD) override bit in one o

Re: [PATCH V3 2/2] PCI: dwc: Add support to configure for ECRC

2020-11-02 Thread Vidya Sagar
On 11/2/2020 7:45 PM, Rob Herring wrote: External email: Use caution opening links or attachments On Thu, Oct 29, 2020 at 12:40 AM Vidya Sagar wrote: DesignWare core has a TLP digest (TD) override bit in one of the control registers of ATU. This bit also needs to be programmed for proper

Re: [PATCH V3 2/2] PCI: dwc: Add support to configure for ECRC

2020-11-02 Thread Rob Herring
On Thu, Oct 29, 2020 at 12:40 AM Vidya Sagar wrote: > > DesignWare core has a TLP digest (TD) override bit in one of the control > registers of ATU. This bit also needs to be programmed for proper ECRC > functionality. This is currently identified as an issue with DesignWare > IP version 4.90a. Th

Re: [PATCH V3 2/2] PCI: dwc: Add support to configure for ECRC

2020-10-29 Thread Vidya Sagar
On 10/30/2020 3:33 AM, Jingoo Han wrote: External email: Use caution opening links or attachments On 10/29/20, 1:40 AM, Vidya Sagar wrote: DesignWare core has a TLP digest (TD) override bit in one of the control registers of ATU. This bit also needs to be programmed for proper ECRC functio

Re: [PATCH V3 2/2] PCI: dwc: Add support to configure for ECRC

2020-10-29 Thread Jingoo Han
On 10/29/20, 1:40 AM, Vidya Sagar wrote: > > DesignWare core has a TLP digest (TD) override bit in one of the control > registers of ATU. This bit also needs to be programmed for proper ECRC > functionality. This is currently identified as an issue with DesignWare > IP version 4.90a. This patch do