On 06/19/2013 11:52 AM, Arnd Bergmann wrote:
On Wednesday 19 June 2013, David Daney wrote:
On 06/19/2013 03:01 AM, Arnd Bergmann wrote:
It's also wrong to use the
__raw_* variant, which is not guaranteed to be atomic and is not
endian-safe.
We do runtime probing and only use this function o
On Wednesday 19 June 2013, David Daney wrote:
> On 06/19/2013 03:01 AM, Arnd Bergmann wrote:
> > It's also wrong to use the
> > __raw_* variant, which is not guaranteed to be atomic and is not
> > endian-safe.
>
> We do runtime probing and only use this function on platforms where it
> is approp
On 06/19/2013 07:10 AM, Heikki Krogerus wrote:
On Tue, Jun 18, 2013 at 12:12:53PM -0700, David Daney wrote:
A few differences needed by OCTEON:
o These are DWC UARTS, but have USR at a different offset.
o OCTEON must have 64-bit wide register accesses, so we have OCTEON
specific register ac
On 06/19/2013 03:01 AM, Arnd Bergmann wrote:
On Tuesday 18 June 2013 12:12:53 David Daney wrote:
+static unsigned int dw8250_serial_inq(struct uart_port *p, int offset)
+{
+ offset <<= p->regshift;
+
+ return (u8)__raw_readq(p->membase + offset);
+}
+
+static void dw8250_serial_outq(
On Tue, Jun 18, 2013 at 12:12:53PM -0700, David Daney wrote:
> A few differences needed by OCTEON:
>
> o These are DWC UARTS, but have USR at a different offset.
>
> o OCTEON must have 64-bit wide register accesses, so we have OCTEON
> specific register accessors.
>
> o No UCV register, so we
On Wed, Jun 19, 2013 at 12:01:06PM +0200, Arnd Bergmann wrote:
> This breaks building on 32 bit architectures as I found on my daily ARM
> builds: __raw_writeq cannot be defined on architectures that don't have
> native 64 bit data access instructions. It's also wrong to use the
> __raw_* variant,
On Tuesday 18 June 2013 12:12:53 David Daney wrote:
> +static unsigned int dw8250_serial_inq(struct uart_port *p, int offset)
> +{
> + offset <<= p->regshift;
> +
> + return (u8)__raw_readq(p->membase + offset);
> +}
> +
> +static void dw8250_serial_outq(struct uart_port *p, int offset,
On Tue, Jun 18, 2013 at 12:12:53PM -0700, David Daney wrote:
> From: David Daney
>
> A few differences needed by OCTEON:
>
> o These are DWC UARTS, but have USR at a different offset.
>
> o OCTEON must have 64-bit wide register accesses, so we have OCTEON
> specific register accessors.
>
> o
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