Re: [PATCH 2/9] RISC-V: Atomic and Locking Code

2017-07-10 Thread Palmer Dabbelt
On Thu, 06 Jul 2017 19:14:25 PDT (-0700), boqun.f...@gmail.com wrote: > On Thu, Jul 06, 2017 at 06:04:13PM -0700, Palmer Dabbelt wrote: > [...] >> >> +#define __smp_load_acquire(p) >> >> \ >> >> +do {

Re: [PATCH 2/9] RISC-V: Atomic and Locking Code

2017-07-10 Thread Palmer Dabbelt
On Fri, 07 Jul 2017 01:08:19 PDT (-0700), pet...@infradead.org wrote: > On Thu, Jul 06, 2017 at 06:04:13PM -0700, Palmer Dabbelt wrote: >> +/* >> + * TODO_RISCV_MEMORY_MODEL: I don't think RISC-V is allowed to perform a >> + * speculative load, but we're going to wait on a formal memory model

Re: [PATCH 2/9] RISC-V: Atomic and Locking Code

2017-07-07 Thread Peter Zijlstra
On Thu, Jul 06, 2017 at 06:04:13PM -0700, Palmer Dabbelt wrote: > > Also probably not true. I _think_ you want a full barrier here, but > > given the total lack of documentation on your end and the fact I've not > > yet read the spinlock (which I suppose is below) I cannot yet state > > more. > >

Re: [PATCH 2/9] RISC-V: Atomic and Locking Code

2017-07-06 Thread Boqun Feng
On Thu, Jul 06, 2017 at 06:04:13PM -0700, Palmer Dabbelt wrote: [...] > >> +#define __smp_load_acquire(p) > >> \ > >> +do { > >> \ > >> + union { typeof(*p) __val; char __c[1]; } __u

Re: [PATCH 2/9] RISC-V: Atomic and Locking Code

2017-07-06 Thread Palmer Dabbelt
On Wed, 05 Jul 2017 01:43:21 PDT (-0700), pet...@infradead.org wrote: > On Tue, Jul 04, 2017 at 12:50:55PM -0700, Palmer Dabbelt wrote: >> +/* >> + * FIXME: I could only find documentation that atomic_{add,sub,inc,dec} are >> + * barrier-free. I'm assuming that and/or/xor have the same constraints

Re: [PATCH 2/9] RISC-V: Atomic and Locking Code

2017-07-06 Thread Peter Zijlstra
On Thu, Jul 06, 2017 at 07:08:33PM +0800, Boqun Feng wrote: > On Wed, Jul 05, 2017 at 10:43:21AM +0200, Peter Zijlstra wrote: > > On Tue, Jul 04, 2017 at 12:50:55PM -0700, Palmer Dabbelt wrote: > > > +/* > > > + * FIXME: I could only find documentation that atomic_{add,sub,inc,dec} > > > are > > >

Re: [PATCH 2/9] RISC-V: Atomic and Locking Code

2017-07-05 Thread Boqun Feng
On Wed, Jul 05, 2017 at 10:43:21AM +0200, Peter Zijlstra wrote: > On Tue, Jul 04, 2017 at 12:50:55PM -0700, Palmer Dabbelt wrote: > > +/* > > + * FIXME: I could only find documentation that atomic_{add,sub,inc,dec} are > > + * barrier-free. I'm assuming that and/or/xor have the same constraints >

Re: [PATCH 2/9] RISC-V: Atomic and Locking Code

2017-07-05 Thread Boqun Feng
On Tue, Jul 04, 2017 at 12:50:55PM -0700, Palmer Dabbelt wrote: [...] > diff --git a/arch/riscv/include/asm/cmpxchg.h > b/arch/riscv/include/asm/cmpxchg.h > new file mode 100644 > index ..81025c056412 > --- /dev/null > +++ b/arch/riscv/include/asm/cmpxchg.h > @@ -0,0 +1,138 @@ > +/* >

Re: [PATCH 2/9] RISC-V: Atomic and Locking Code

2017-07-05 Thread Peter Zijlstra
On Tue, Jul 04, 2017 at 12:50:55PM -0700, Palmer Dabbelt wrote: > +/* > + * FIXME: I could only find documentation that atomic_{add,sub,inc,dec} are > + * barrier-free. I'm assuming that and/or/xor have the same constraints as > the > + * others. > + */ Yes.. we have new documentation in the wor