On Tue, Jul 14, 2020 at 09:41:29PM -0700, Sean Christopherson wrote:
> On Tue, Jul 14, 2020 at 05:39:30AM +, Andersen, John wrote:
> > With regards to FSGSBASE, are we open to validating and adding that to the
> > DEFAULT set as a part of a separate patchset? This patchset is focused on
> > rep
On Tue, Jul 14, 2020 at 05:39:30AM +, Andersen, John wrote:
> With regards to FSGSBASE, are we open to validating and adding that to the
> DEFAULT set as a part of a separate patchset? This patchset is focused on
> replicating the functionality we already have natively.
Kees added FSGSBASE pin
On Thu, Jul 09, 2020 at 09:27:43AM -0700, Andy Lutomirski wrote:
> On Thu, Jul 9, 2020 at 9:22 AM Dave Hansen wrote:
> >
> > On 7/9/20 9:07 AM, Andy Lutomirski wrote:
> > > On Thu, Jul 9, 2020 at 8:56 AM Dave Hansen wrote:
> > >> On 7/9/20 8:44 AM, Andersen, John wrote:
> > >>> Bits which
On Thu, Jul 09, 2020 at 09:27:43AM -0700, Andy Lutomirski wrote:
> On Thu, Jul 9, 2020 at 9:22 AM Dave Hansen wrote:
> >
> > On 7/9/20 9:07 AM, Andy Lutomirski wrote:
> > > On Thu, Jul 9, 2020 at 8:56 AM Dave Hansen wrote:
> > >> On 7/9/20 8:44 AM, Andersen, John wrote:
> > >>> Bits which
On Thu, Jul 09, 2020 at 09:22:09AM -0700, Dave Hansen wrote:
> On 7/9/20 9:07 AM, Andy Lutomirski wrote:
> > On Thu, Jul 9, 2020 at 8:56 AM Dave Hansen wrote:
> >> On 7/9/20 8:44 AM, Andersen, John wrote:
> >>> Bits which are allowed to be pinned default to WP for CR0 and
> >>> SMEP,
> >>
On 7/9/20 9:07 AM, Andy Lutomirski wrote:
> On Thu, Jul 9, 2020 at 8:56 AM Dave Hansen wrote:
>> On 7/9/20 8:44 AM, Andersen, John wrote:
>>> Bits which are allowed to be pinned default to WP for CR0 and SMEP,
>>> SMAP, and UMIP for CR4.
>> I think it also makes sense to have FSGSB
On 7/9/20 8:44 AM, Andersen, John wrote:
>
> Bits which are allowed to be pinned default to WP for CR0 and SMEP,
> SMAP, and UMIP for CR4.
I think it also makes sense to have FSGSBASE in this set.
I know it hasn't been tested, but I think we should do the legwork to
test it. If
On Tue, Jul 07, 2020 at 11:51:54PM +0200, Paolo Bonzini wrote:
> On 07/07/20 23:48, Dave Hansen wrote:
> > On 7/7/20 2:12 PM, Sean Christopherson wrote:
> > Let's say Intel loses its marbles and adds a CR4 bit that lets userspace
> > write to kernel memory. Linux won't set it, but an attac
On 07/07/20 23:48, Dave Hansen wrote:
> On 7/7/20 2:12 PM, Sean Christopherson wrote:
> Let's say Intel loses its marbles and adds a CR4 bit that lets userspace
> write to kernel memory. Linux won't set it, but an attacker would go
> after it, first thing.
>> That's an orthogonal to pi
On 7/7/20 2:12 PM, Sean Christopherson wrote:
Let's say Intel loses its marbles and adds a CR4 bit that lets userspace
write to kernel memory. Linux won't set it, but an attacker would go
after it, first thing.
> That's an orthogonal to pinning. KVM never lets the guest set CR4 bit
On Thu, Jun 18, 2020 at 07:51:10AM -0700, Dave Hansen wrote:
> On 6/18/20 7:43 AM, Andersen, John wrote:
> > On Thu, Jun 18, 2020 at 07:18:09AM -0700, Dave Hansen wrote:
> >> On 6/17/20 12:07 PM, John Andersen wrote:
> >>> +#define KVM_CR0_PIN_ALLOWED (X86_CR0_WP)
> >>> +#define KVM_CR4_PIN_AL
On 6/18/20 7:43 AM, Andersen, John wrote:
> On Thu, Jun 18, 2020 at 07:18:09AM -0700, Dave Hansen wrote:
>> On 6/17/20 12:07 PM, John Andersen wrote:
>>> +#define KVM_CR0_PIN_ALLOWED(X86_CR0_WP)
>>> +#define KVM_CR4_PIN_ALLOWED(X86_CR4_SMEP | X86_CR4_SMAP |
>>> X86_CR4_UMIP)
>>
>>
On Thu, Jun 18, 2020 at 07:18:09AM -0700, Dave Hansen wrote:
> On 6/17/20 12:07 PM, John Andersen wrote:
> > +#define KVM_CR0_PIN_ALLOWED(X86_CR0_WP)
> > +#define KVM_CR4_PIN_ALLOWED(X86_CR4_SMEP | X86_CR4_SMAP |
> > X86_CR4_UMIP)
>
> Why *is* there an allowed set? Why don't we j
On 6/17/20 12:07 PM, John Andersen wrote:
> +#define KVM_CR0_PIN_ALLOWED (X86_CR0_WP)
> +#define KVM_CR4_PIN_ALLOWED (X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP)
Why *is* there an allowed set? Why don't we just allow everything?
Shouldn't we also pin any unknown bits? The CR4.FSGSBASE bit is
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