On 5/6/2020 3:40 PM, Dilip Kota wrote:
On 5/5/2020 7:23 PM, Mark Brown wrote:
On Mon, May 04, 2020 at 06:15:47PM +0800, Dilip Kota wrote:
On 4/29/2020 8:13 PM, Mark Brown wrote:
I just tried to get the history of removing workqueue in SPI driver, on
GRX500 (earlier chipset of LGM) the SPI t
On 5/5/2020 7:23 PM, Mark Brown wrote:
On Mon, May 04, 2020 at 06:15:47PM +0800, Dilip Kota wrote:
On 4/29/2020 8:13 PM, Mark Brown wrote:
I just tried to get the history of removing workqueue in SPI driver, on
GRX500 (earlier chipset of LGM) the SPI transfers got timedout with
workqueues d
On Mon, May 04, 2020 at 06:15:47PM +0800, Dilip Kota wrote:
> On 4/29/2020 8:13 PM, Mark Brown wrote:
> > > Workqueue has a higher chances of causing SPI transfers timedout.
> > because...?
> I just tried to get the history of removing workqueue in SPI driver, on
> GRX500 (earlier chipset of LGM)
On 4/29/2020 8:13 PM, Mark Brown wrote:
On Wed, Apr 29, 2020 at 04:20:53PM +0800, Dilip Kota wrote:
On 4/28/2020 7:10 PM, Daniel Schwierzeck wrote:
actually there is no real bottom half. Reading or writing the FIFOs is
fast and is therefore be done in hard IRQ context. But as the comment
Doi
On Wed, Apr 29, 2020 at 03:20:21PM +0800, Dilip Kota wrote:
> On 4/28/2020 6:00 PM, Mark Brown wrote:
> > The change was not entirely clear, I was having trouble convincing
> > myself that all the transformations were OK partly because I kept on
> > finding little extra changes in there and partly
On Wed, Apr 29, 2020 at 04:20:53PM +0800, Dilip Kota wrote:
> On 4/28/2020 7:10 PM, Daniel Schwierzeck wrote:
> > actually there is no real bottom half. Reading or writing the FIFOs is
> > fast and is therefore be done in hard IRQ context. But as the comment
> Doing FIFO r/w in threaded irqs shou
On 4/28/2020 7:30 PM, Hauke Mehrtens wrote:
On 4/28/20 1:10 PM, Daniel Schwierzeck wrote:
Am 24.04.20 um 12:42 schrieb Dilip Kota:
...
Hi,
The Interrupt controller found on Danube till xrx300 which is probably
from Infineon like this SPI controller IP acknowledges the interrupts
also insi
On 4/28/2020 7:10 PM, Daniel Schwierzeck wrote:
Am 24.04.20 um 12:42 schrieb Dilip Kota:
Synchronize tx, rx and error interrupts by registering to the
same interrupt handler. Interrupt handler will recognize and process
the appropriate interrupt on the basis of interrupt status register.
Also
On 4/28/2020 6:00 PM, Mark Brown wrote:
On Tue, Apr 28, 2020 at 01:39:06PM +0800, Dilip Kota wrote:
Do you suggest to use different ISRs for multiple interrupt lines and single
ISR for single interrupt line? I see, this results in writing repetitive
code lines.
It looks like the shared case
On 4/28/20 1:10 PM, Daniel Schwierzeck wrote:
>
>
> Am 24.04.20 um 12:42 schrieb Dilip Kota:
>> Synchronize tx, rx and error interrupts by registering to the
>> same interrupt handler. Interrupt handler will recognize and process
>> the appropriate interrupt on the basis of interrupt status regis
Am 24.04.20 um 12:42 schrieb Dilip Kota:
> Synchronize tx, rx and error interrupts by registering to the
> same interrupt handler. Interrupt handler will recognize and process
> the appropriate interrupt on the basis of interrupt status register.
> Also, establish synchronization between the int
On Tue, Apr 28, 2020 at 01:39:06PM +0800, Dilip Kota wrote:
> Do you suggest to use different ISRs for multiple interrupt lines and single
> ISR for single interrupt line? I see, this results in writing repetitive
> code lines.
It looks like the shared case is mainly a handler that calls the two
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