On Mon, Jul 23, 2012 at 06:48:12PM +0100, Stephen Warren wrote:
> On 07/08/2012 03:18 AM, Catalin Marinas wrote:
> > On Fri, Jul 06, 2012 at 10:32:54PM +0100, Stephen Warren wrote:
> >> On 07/06/2012 03:05 PM, Catalin Marinas wrote:
> >>> The patch adds the kernel booting and the initial setup code
On 07/08/2012 03:18 AM, Catalin Marinas wrote:
> On Fri, Jul 06, 2012 at 10:32:54PM +0100, Stephen Warren wrote:
>> On 07/06/2012 03:05 PM, Catalin Marinas wrote:
>>> The patch adds the kernel booting and the initial setup code.
>>> Documentation/aarch64/booting.txt describes the booting protocol o
Hi Catalin,
On 07/20/2012 09:48 AM, Catalin Marinas wrote:
> On Thu, Jul 19, 2012 at 06:31:07PM +0100, Christopher Covington wrote:
>> On 07/18/2012 02:57 AM, Jon Masters wrote:
>>> On 07/06/2012 05:05 PM, Catalin Marinas wrote:
>>>
+- CPU mode
+ All forms of interrupts must be masked i
On Fri, Jul 20, 2012 at 02:47:36PM +0100, Christopher Covington wrote:
> On 07/20/2012 03:10 AM, Jon Masters wrote:
> > Unless you enter at EL2 you can never install a hypervisor. That's the
> > reason for the requirement for generally entering at EL2 when possible.
>
> That brief explanation woul
On Thu, Jul 19, 2012 at 06:31:07PM +0100, Christopher Covington wrote:
> On 07/18/2012 02:57 AM, Jon Masters wrote:
> > On 07/06/2012 05:05 PM, Catalin Marinas wrote:
> >
> >> +- CPU mode
> >> + All forms of interrupts must be masked in PSTATE.DAIF (Debug, SError,
> >> + IRQ and FIQ).
> >> + Th
Hi Jon,
On 07/20/2012 03:10 AM, Jon Masters wrote:
> On 07/19/2012 01:31 PM, Christopher Covington wrote:
>> On 07/18/2012 02:57 AM, Jon Masters wrote:
>>> On 07/06/2012 05:05 PM, Catalin Marinas wrote:
>>>
+- CPU mode
+ All forms of interrupts must be masked in PSTATE.DAIF (Debug, SErr
On Fri, Jul 20, 2012 at 01:32:39PM +0100, Geert Uytterhoeven wrote:
> On Fri, Jul 20, 2012 at 12:52 PM, Catalin Marinas
> wrote:
> > On Fri, Jul 20, 2012 at 09:28:12AM +0100, Arnd Bergmann wrote:
> >> On Friday 20 July 2012, Jon Masters wrote:
> >> > > I think it would be best to list the technica
Hi Catalin,
On Fri, Jul 20, 2012 at 12:52 PM, Catalin Marinas
wrote:
> On Fri, Jul 20, 2012 at 09:28:12AM +0100, Arnd Bergmann wrote:
>> On Friday 20 July 2012, Jon Masters wrote:
>> > > I think it would be best to list the technical limitations, from the
>> > > kernel's perspective, of the unsup
On Fri, Jul 20, 2012 at 09:28:12AM +0100, Arnd Bergmann wrote:
> On Friday 20 July 2012, Jon Masters wrote:
> > > I think it would be best to list the technical limitations, from the
> > > kernel's perspective, of the unsupported exception levels and the
> > > advantages of the supported exception
On Friday 20 July 2012, Jon Masters wrote:
> > I think it would be best to list the technical limitations, from the
> > kernel's perspective, of the unsupported exception levels and the
> > advantages of the supported exception levels here. If you want to guide
> > system builders towards EL2, I th
On 07/18/2012 05:07 AM, Will Deacon wrote:
> On Wed, Jul 18, 2012 at 07:57:47AM +0100, Jon Masters wrote:
>> On 07/06/2012 05:05 PM, Catalin Marinas wrote:
>>
>>> +- CPU mode
>>> + All forms of interrupts must be masked in PSTATE.DAIF (Debug, SError,
>>> + IRQ and FIQ).
>>> + The CPU must be in
On 07/19/2012 01:31 PM, Christopher Covington wrote:
> On 07/18/2012 02:57 AM, Jon Masters wrote:
>> On 07/06/2012 05:05 PM, Catalin Marinas wrote:
>>
>>> +- CPU mode
>>> + All forms of interrupts must be masked in PSTATE.DAIF (Debug, SError,
>>> + IRQ and FIQ).
>>> + The CPU must be in either E
On 07/18/2012 02:57 AM, Jon Masters wrote:
> On 07/06/2012 05:05 PM, Catalin Marinas wrote:
>
>> +- CPU mode
>> + All forms of interrupts must be masked in PSTATE.DAIF (Debug, SError,
>> + IRQ and FIQ).
>> + The CPU must be in either EL2 (RECOMMENDED) or non-secure EL1.
Why not secure EL1?
>
On Wed, Jul 18, 2012 at 07:57:47AM +0100, Jon Masters wrote:
> On 07/06/2012 05:05 PM, Catalin Marinas wrote:
>
> > +- CPU mode
> > + All forms of interrupts must be masked in PSTATE.DAIF (Debug, SError,
> > + IRQ and FIQ).
> > + The CPU must be in either EL2 (RECOMMENDED) or non-secure EL1.
>
On 07/06/2012 05:05 PM, Catalin Marinas wrote:
> +- CPU mode
> + All forms of interrupts must be masked in PSTATE.DAIF (Debug, SError,
> + IRQ and FIQ).
> + The CPU must be in either EL2 (RECOMMENDED) or non-secure EL1.
Even though this stuff is likely to be replaced with the result of some
of
On Fri, Jul 06, 2012 at 10:32:54PM +0100, Stephen Warren wrote:
> On 07/06/2012 03:05 PM, Catalin Marinas wrote:
> > The patch adds the kernel booting and the initial setup code.
> > Documentation/aarch64/booting.txt describes the booting protocol on the
> > AArch64 Linux kernel. This is subject to
On 07/06/2012 03:05 PM, Catalin Marinas wrote:
> The patch adds the kernel booting and the initial setup code.
> Documentation/aarch64/booting.txt describes the booting protocol on the
> AArch64 Linux kernel. This is subject to change following the work on
> boot standardisation, ACPI.
> diff --gi
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