Re: [PATCH 02/12] pinctrl: Add core pinctrl support for Aspeed SoCs

2016-08-14 Thread Andrew Jeffery
On Sat, 2016-08-13 at 10:58 +1000, Benjamin Herrenschmidt wrote: > On Fri, 2016-08-12 at 15:18 +0200, Linus Walleij wrote: > > > > I would probably prefer that option (introduce another field) > > but you should make the overall decision, it's no strong opinion > > from my side. > > > > > > > >

Re: [PATCH 02/12] pinctrl: Add core pinctrl support for Aspeed SoCs

2016-08-12 Thread Benjamin Herrenschmidt
On Fri, 2016-08-12 at 15:18 +0200, Linus Walleij wrote: > I would probably prefer that option (introduce another field) > but you should make the overall decision, it's no strong opinion > from my side. > > > Would it be acceptable to document that requirement? It might make it a bit less nasty (

Re: [PATCH 02/12] pinctrl: Add core pinctrl support for Aspeed SoCs

2016-08-12 Thread Linus Walleij
On Fri, Aug 12, 2016 at 2:33 AM, Andrew Jeffery wrote: >> > + >> > + while (*exprs) { >> > + if (strncmp((*exprs)->signal, "GPIO", 4) == 0) >> > + return true; >> This looks a bit fragile and hard to debug. Do you have some better >> idea of how to do thi

Re: [PATCH 02/12] pinctrl: Add core pinctrl support for Aspeed SoCs

2016-08-11 Thread Andrew Jeffery
On Thu, 2016-08-11 at 10:41 +0200, Linus Walleij wrote: > On Wed, Jul 20, 2016 at 7:58 AM, Andrew Jeffery wrote: > > > > > --- a/arch/arm/mach-aspeed/Kconfig > > +++ b/arch/arm/mach-aspeed/Kconfig > > @@ -5,6 +5,7 @@ menuconfig ARCH_ASPEED > > select WATCHDOG > > select ASPEED_WA

Re: [PATCH 02/12] pinctrl: Add core pinctrl support for Aspeed SoCs

2016-08-11 Thread Linus Walleij
On Wed, Jul 20, 2016 at 7:58 AM, Andrew Jeffery wrote: > --- a/arch/arm/mach-aspeed/Kconfig > +++ b/arch/arm/mach-aspeed/Kconfig > @@ -5,6 +5,7 @@ menuconfig ARCH_ASPEED > select WATCHDOG > select ASPEED_WATCHDOG > select MOXART_TIMER > + select PINCTRL > hel

Re: [PATCH 02/12] pinctrl: Add core pinctrl support for Aspeed SoCs

2016-07-21 Thread Joel Stanley
On Wed, Jul 20, 2016 at 3:28 PM, Andrew Jeffery wrote: > The Aspeed SoCs provide typically more than 200 pins for GPIO and other > functions. The signal enabled on a pin is determined on a priority > basis, where a given pin can provide a number of different signal types. > > In addition to the pr