Re: [PATCH 0/3] PCI: rockchip: assert PERST# in S3

2017-10-13 Thread Brian Norris
Hi Bjorn, One piece of information to add: On Thu, Oct 12, 2017 at 11:27 PM, Brian Norris wrote: > On Thu, Oct 12, 2017 at 10:15:23PM -0500, Bjorn Helgaas wrote: > > Is this a hole in those specs? Is this something that needs to be > > clarified by the PCI-SIG to improve interoperability? > > A

Re: [PATCH 0/3] PCI: rockchip: assert PERST# in S3

2017-10-12 Thread Brian Norris
Hi Bjorn, On Thu, Oct 12, 2017 at 10:15:23PM -0500, Bjorn Helgaas wrote: > On Thu, Oct 12, 2017 at 01:52:17PM -0700, Brian Norris wrote: > > Hi, > > > > This patch series should mostly be self-descriptive, but it's motivated by > > the > > fact that I've found differing requirements from PCIe en

Re: [PATCH 0/3] PCI: rockchip: assert PERST# in S3

2017-10-12 Thread Bjorn Helgaas
On Thu, Oct 12, 2017 at 01:52:17PM -0700, Brian Norris wrote: > Hi, > > This patch series should mostly be self-descriptive, but it's motivated by the > fact that I've found differing requirements from PCIe endpoint makers > regarding > the state of PERST# when in system suspend (S3). Additionall

Re: [PATCH 0/3] PCI: rockchip: assert PERST# in S3

2017-10-12 Thread Doug Anderson
Hi, On Thu, Oct 12, 2017 at 1:52 PM, Brian Norris wrote: > Hi, > > This patch series should mostly be self-descriptive, but it's motivated by the > fact that I've found differing requirements from PCIe endpoint makers > regarding > the state of PERST# when in system suspend (S3). Additionally, s