On 19/12/17 06:55, Linu Cherian wrote:
> Hi Marc,
>
> On Mon Dec 18, 2017 at 03:39:22PM +, Marc Zyngier wrote:
>> Thanks for putting me in the loop Robin.
>>
>> On 18/12/17 14:48, Robin Murphy wrote:
>>> On 10/12/17 02:35, Linu Cherian wrote:
Hi,
On Fri Aug 04, 2017 at 03:5
Hi Marc,
On Mon Dec 18, 2017 at 03:39:22PM +, Marc Zyngier wrote:
> Thanks for putting me in the loop Robin.
>
> On 18/12/17 14:48, Robin Murphy wrote:
> > On 10/12/17 02:35, Linu Cherian wrote:
> >> Hi,
> >>
> >>
> >> On Fri Aug 04, 2017 at 03:59:12PM -0400, Neil Leeder wrote:
> >>> This add
Hi Robin,
On Mon Dec 18, 2017 at 02:48:14PM +, Robin Murphy wrote:
> On 10/12/17 02:35, Linu Cherian wrote:
> >Hi,
> >
> >
> >On Fri Aug 04, 2017 at 03:59:12PM -0400, Neil Leeder wrote:
> >>This adds a driver for the SMMUv3 PMU into the perf framework.
> >>It includes an IORT update to support
Thanks for putting me in the loop Robin.
On 18/12/17 14:48, Robin Murphy wrote:
> On 10/12/17 02:35, Linu Cherian wrote:
>> Hi,
>>
>>
>> On Fri Aug 04, 2017 at 03:59:12PM -0400, Neil Leeder wrote:
>>> This adds a driver for the SMMUv3 PMU into the perf framework.
>>> It includes an IORT update to
On 10/12/17 02:35, Linu Cherian wrote:
Hi,
On Fri Aug 04, 2017 at 03:59:12PM -0400, Neil Leeder wrote:
This adds a driver for the SMMUv3 PMU into the perf framework.
It includes an IORT update to support PM Counter Groups.
In one of Cavium's upcoming SOC, SMMU PMCG implementation is such a
Hi,
On Fri Aug 04, 2017 at 03:59:12PM -0400, Neil Leeder wrote:
> This adds a driver for the SMMUv3 PMU into the perf framework.
> It includes an IORT update to support PM Counter Groups.
>
In one of Cavium's upcoming SOC, SMMU PMCG implementation is such a way
that platform bus id (Device ID in
Hi Yury,
On 10/31/2017 7:33 PM, Yury Norov wrote:
> Hi Neil,
>
> On Fri, Aug 04, 2017 at 03:59:12PM -0400, Neil Leeder wrote:
>> This adds a driver for the SMMUv3 PMU into the perf framework.
>> It includes an IORT update to support PM Counter Groups.
>>
>> IORT has no mechanism for determining d
Hi Neil,
On Fri, Aug 04, 2017 at 03:59:12PM -0400, Neil Leeder wrote:
> This adds a driver for the SMMUv3 PMU into the perf framework.
> It includes an IORT update to support PM Counter Groups.
>
> IORT has no mechanism for determining device names so PMUs
> are named based on their physical addr
On 2017/10/12 19:05, Lorenzo Pieralisi wrote:
> On Thu, Oct 12, 2017 at 06:58:33PM +0800, Hanjun Guo wrote:
>> On 2017/8/11 11:28, Leeder, Neil wrote:
>>> On 8/9/2017 9:26 PM, Hanjun Guo wrote:
> On 2017/8/9 23:48, Leeder, Neil wrote:
>>>drivers/perf/Kconfig | 9 +
>>>
On Thu, Oct 12, 2017 at 06:58:33PM +0800, Hanjun Guo wrote:
> On 2017/8/11 11:28, Leeder, Neil wrote:
> > On 8/9/2017 9:26 PM, Hanjun Guo wrote:
> >> > On 2017/8/9 23:48, Leeder, Neil wrote:
> > drivers/perf/Kconfig | 9 +
> > drivers/perf/Makefile | 1 +
On 2017/8/11 11:28, Leeder, Neil wrote:
> On 8/9/2017 9:26 PM, Hanjun Guo wrote:
>> > On 2017/8/9 23:48, Leeder, Neil wrote:
> drivers/perf/Kconfig | 9 +
> drivers/perf/Makefile | 1 +
> drivers/perf/arm_smmuv3_pmu.c | 823
>
On 8/9/2017 9:26 PM, Hanjun Guo wrote:
> On 2017/8/9 23:48, Leeder, Neil wrote:
drivers/perf/Kconfig | 9 +
drivers/perf/Makefile | 1 +
drivers/perf/arm_smmuv3_pmu.c | 823
++
include/acpi/actbl2.h
On 2017/8/9 23:48, Leeder, Neil wrote:
drivers/perf/Kconfig | 9 +
drivers/perf/Makefile | 1 +
drivers/perf/arm_smmuv3_pmu.c | 823
++
include/acpi/actbl2.h | 9 +-
Do you have the acpica support code? I'm currently
Hi Hanjun,
On 8/9/2017 3:56 AM, Hanjun Guo wrote:
> Hi Neil,
>
> On 2017/8/5 3:59, Neil Leeder wrote:
>> This adds a driver for the SMMUv3 PMU into the perf framework.
>> It includes an IORT update to support PM Counter Groups.
>>
>> IORT has no mechanism for determining device names so PMUs
>> a
Hi Neil,
On 2017/8/5 3:59, Neil Leeder wrote:
This adds a driver for the SMMUv3 PMU into the perf framework.
It includes an IORT update to support PM Counter Groups.
IORT has no mechanism for determining device names so PMUs
are named based on their physical address.
Tested on Qualcomm QDF2400
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