Hi KyongHo and David,
On 07.08.20 09:08, Pekka Enberg wrote:
> > > I think having more knowledge of DRAM controller details in the OS
> > > would be potentially beneficial for better page allocation policy, so
> > > maybe try come up with something more generic, even if the fallback to
> > > provi
On Mon, Aug 10, 2020 at 09:32:18AM +0200, David Hildenbrand wrote:
> On 07.08.20 09:08, Pekka Enberg wrote:
> > Hi Cho and David,
> >
> > On Mon, Aug 3, 2020 at 10:57 AM David Hildenbrand wrote:
> >>
> >> On 03.08.20 08:10, pullip@samsung.com wrote:
> >>> From: Cho KyongHo
> >>>
> >>> LPDDR5
On 07.08.20 09:08, Pekka Enberg wrote:
> Hi Cho and David,
>
> On Mon, Aug 3, 2020 at 10:57 AM David Hildenbrand wrote:
>>
>> On 03.08.20 08:10, pullip@samsung.com wrote:
>>> From: Cho KyongHo
>>>
>>> LPDDR5 introduces rank switch delay. If three successive DRAM accesses
>>> happens and the
Hi Cho and David,
On Mon, Aug 3, 2020 at 10:57 AM David Hildenbrand wrote:
>
> On 03.08.20 08:10, pullip@samsung.com wrote:
> > From: Cho KyongHo
> >
> > LPDDR5 introduces rank switch delay. If three successive DRAM accesses
> > happens and the first and the second ones access one rank and t
On Tue, Aug 04, 2020 at 11:12:55AM +0200, Vlastimil Babka wrote:
> On 8/4/20 4:35 AM, Cho KyongHo wrote:
> > On Mon, Aug 03, 2020 at 05:45:55PM +0200, Vlastimil Babka wrote:
> >> On 8/3/20 9:57 AM, David Hildenbrand wrote:
> >> > On 03.08.20 08:10, pullip@samsung.com wrote:
> >> >> From: Cho Ky
On 8/4/20 4:35 AM, Cho KyongHo wrote:
> On Mon, Aug 03, 2020 at 05:45:55PM +0200, Vlastimil Babka wrote:
>> On 8/3/20 9:57 AM, David Hildenbrand wrote:
>> > On 03.08.20 08:10, pullip@samsung.com wrote:
>> >> From: Cho KyongHo
>> >>
>> >> LPDDR5 introduces rank switch delay. If three successiv
On Mon, Aug 03, 2020 at 05:45:55PM +0200, Vlastimil Babka wrote:
> On 8/3/20 9:57 AM, David Hildenbrand wrote:
> > On 03.08.20 08:10, pullip@samsung.com wrote:
> >> From: Cho KyongHo
> >>
> >> LPDDR5 introduces rank switch delay. If three successive DRAM accesses
> >> happens and the first an
On 8/3/20 9:57 AM, David Hildenbrand wrote:
> On 03.08.20 08:10, pullip@samsung.com wrote:
>> From: Cho KyongHo
>>
>> LPDDR5 introduces rank switch delay. If three successive DRAM accesses
>> happens and the first and the second ones access one rank and the last
>> access happens on the other
Hi,
On Mon, Aug 03, 2020 at 09:57:10AM +0200, David Hildenbrand wrote:
> On 03.08.20 08:10, pullip@samsung.com wrote:
> > From: Cho KyongHo
> >
> > LPDDR5 introduces rank switch delay. If three successive DRAM accesses
> > happens and the first and the second ones access one rank and the las
On 03.08.20 08:10, pullip@samsung.com wrote:
> From: Cho KyongHo
>
> LPDDR5 introduces rank switch delay. If three successive DRAM accesses
> happens and the first and the second ones access one rank and the last
> access happens on the other rank, the latency of the last access will
> be lon
10 matches
Mail list logo