On Tue, Oct 22, 2013 at 06:28:13PM +0200, Sebastian Andrzej Siewior wrote:
> On 10/22/2013 05:48 PM, Lee Jones wrote:
> > On Tue, 22 Oct 2013, Sebastian Andrzej Siewior wrote:
> >
> >> On 08/07/2013 10:40 AM, Lee Jones wrote:
> >>> On Mon, 05 Aug 2013, Zubair Lutfullah wrote:
> >>>
> Reg_cach
On Tue, 22 Oct 2013, Sebastian Andrzej Siewior wrote:
> On 10/22/2013 07:06 PM, Lee Jones wrote:
> > Hmm.. I'm starting to see what you mean.
> >
> > So what's the point of the read before write then?
> >
> > Why don't you use the cache all of the time?
>
> I'm waiting for Zabair for this. The
On 10/22/2013 07:06 PM, Lee Jones wrote:
> Hmm.. I'm starting to see what you mean.
>
> So what's the point of the read before write then?
>
> Why don't you use the cache all of the time?
I'm waiting for Zabair for this. The last thing he said is that he is
going to have a wedding which might in
On Tue, 22 Oct 2013, Sebastian Andrzej Siewior wrote:
> On 10/22/2013 06:05 PM, Lee Jones wrote:
> >> I added reg_se_cache to cache the content of REG_SE once and
> >> synchronize it among TSC & ADC access. REG_SE is set to 0 by the HW
> >> after "work" has been done. So you need to know the old v
On 10/22/2013 06:05 PM, Lee Jones wrote:
>> I added reg_se_cache to cache the content of REG_SE once and
>> synchronize it among TSC & ADC access. REG_SE is set to 0 by the HW
>> after "work" has been done. So you need to know the old value or TSC may
>> disable ADC and the other way around.
>
> Y
On 10/22/2013 05:48 PM, Lee Jones wrote:
> On Tue, 22 Oct 2013, Sebastian Andrzej Siewior wrote:
>
>> On 08/07/2013 10:40 AM, Lee Jones wrote:
>>> On Mon, 05 Aug 2013, Zubair Lutfullah wrote:
>>>
Reg_cache variable is used to lock step enable register
from being accessed and written by b
On Tue, 22 Oct 2013, Sebastian Andrzej Siewior wrote:
> On 08/07/2013 10:40 AM, Lee Jones wrote:
> > On Mon, 05 Aug 2013, Zubair Lutfullah wrote:
> >
> >> Reg_cache variable is used to lock step enable register
> >> from being accessed and written by both TSC and ADC
> >> at the same time.
> >> H
On Tue, 22 Oct 2013, Sebastian Andrzej Siewior wrote:
> On 08/07/2013 10:40 AM, Lee Jones wrote:
> > On Mon, 05 Aug 2013, Zubair Lutfullah wrote:
> >
> >> Reg_cache variable is used to lock step enable register
> >> from being accessed and written by both TSC and ADC
> >> at the same time.
> >> H
On 08/07/2013 10:40 AM, Lee Jones wrote:
> On Mon, 05 Aug 2013, Zubair Lutfullah wrote:
>
>> Reg_cache variable is used to lock step enable register
>> from being accessed and written by both TSC and ADC
>> at the same time.
>> However, it isn't updated anywhere in the code at all.
>>
>> If both T
On Mon, 05 Aug 2013, Zubair Lutfullah wrote:
> Reg_cache variable is used to lock step enable register
> from being accessed and written by both TSC and ADC
> at the same time.
> However, it isn't updated anywhere in the code at all.
>
> If both TSC and ADC are used, eventually 1 is always
>
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