Quoting Stephen Boyd (2019-07-16 16:47:07)
> Quoting Vivek Gautam (2019-06-12 02:26:20)
> >
> >
> > On 6/11/2019 4:51 AM, Stephen Boyd wrote:
> > > hardware signal like the NS bit and/or the Execution Level. Hopefully
> > > it's a config and then our difference from MTP can be minimized.
> >
> >
Quoting Vivek Gautam (2019-06-12 02:26:20)
>
>
> On 6/11/2019 4:51 AM, Stephen Boyd wrote:
> > hardware signal like the NS bit and/or the Execution Level. Hopefully
> > it's a config and then our difference from MTP can be minimized.
>
> I don't think SMMU limits any such programming of SIDs. It
On 6/11/2019 4:51 AM, Stephen Boyd wrote:
Quoting Vivek Gautam (2019-06-06 04:17:16)
Hi Stephen,
On Thu, Jun 6, 2019 at 2:27 AM Stephen Boyd wrote:
Quoting Vivek Gautam (2019-06-04 21:55:26)
Cheza will throw faults for anything that is programmed with TZ on mtp
as all of that should be h
Quoting Vivek Gautam (2019-06-06 04:17:16)
> Hi Stephen,
>
> On Thu, Jun 6, 2019 at 2:27 AM Stephen Boyd wrote:
> >
> > Quoting Vivek Gautam (2019-06-04 21:55:26)
> >
> > >
> > > Cheza will throw faults for anything that is programmed with TZ on mtp
> > > as all of that should be handled in HLOS.
On 06/06/2019 13:17, Vivek Gautam wrote:
> <&apps_smmu 0x6c0 0x3> // for both 0x6c0 (TZ) and 0x6c3 (HLOS)
Another possibility is to list both:
<&apps_smmu 0x6c0 0x0>
<&apps_smmu 0x6c3 0x0>
which leaves 0x6c1 and 0x6c2 out of the picture, and makes 0x6c3
appear explicitly (for
Hi Stephen,
On Thu, Jun 6, 2019 at 2:27 AM Stephen Boyd wrote:
>
> Quoting Vivek Gautam (2019-06-04 21:55:26)
> > On Wed, Jun 5, 2019 at 4:16 AM Stephen Boyd wrote:
> > >
> > > Quoting Bjorn Andersson (2019-06-04 15:37:00)
> > > > On Tue 04 Jun 15:29 PDT 2019, Stephen Boyd wrote:
> > > >
> > > >
Quoting Vivek Gautam (2019-06-04 21:55:26)
> On Wed, Jun 5, 2019 at 4:16 AM Stephen Boyd wrote:
> >
> > Quoting Bjorn Andersson (2019-06-04 15:37:00)
> > > On Tue 04 Jun 15:29 PDT 2019, Stephen Boyd wrote:
> > >
> > > > The SMMU that sits in front of the QUP needs to be programmed properly
> > > >
On Wed, Jun 5, 2019 at 4:16 AM Stephen Boyd wrote:
>
> Quoting Bjorn Andersson (2019-06-04 15:37:00)
> > On Tue 04 Jun 15:29 PDT 2019, Stephen Boyd wrote:
> >
> > > The SMMU that sits in front of the QUP needs to be programmed properly
> > > so that the i2c geni driver can allocate DMA descriptors
On Tue 04 Jun 15:46 PDT 2019, Stephen Boyd wrote:
> Quoting Bjorn Andersson (2019-06-04 15:37:00)
> > On Tue 04 Jun 15:29 PDT 2019, Stephen Boyd wrote:
> >
> > > The SMMU that sits in front of the QUP needs to be programmed properly
> > > so that the i2c geni driver can allocate DMA descriptors.
On Tue 04 Jun 15:48 PDT 2019, Doug Anderson wrote:
> Hi,
>
> On Tue, Jun 4, 2019 at 3:37 PM Bjorn Andersson
> wrote:
> >
> > On Tue 04 Jun 15:29 PDT 2019, Stephen Boyd wrote:
> >
> > > The SMMU that sits in front of the QUP needs to be programmed properly
> > > so that the i2c geni driver can al
Hi,
On Tue, Jun 4, 2019 at 3:37 PM Bjorn Andersson
wrote:
>
> On Tue 04 Jun 15:29 PDT 2019, Stephen Boyd wrote:
>
> > The SMMU that sits in front of the QUP needs to be programmed properly
> > so that the i2c geni driver can allocate DMA descriptors. Failure to do
> > this leads to faults when us
Quoting Bjorn Andersson (2019-06-04 15:37:00)
> On Tue 04 Jun 15:29 PDT 2019, Stephen Boyd wrote:
>
> > The SMMU that sits in front of the QUP needs to be programmed properly
> > so that the i2c geni driver can allocate DMA descriptors. Failure to do
> > this leads to faults when using devices suc
On Tue 04 Jun 15:29 PDT 2019, Stephen Boyd wrote:
> The SMMU that sits in front of the QUP needs to be programmed properly
> so that the i2c geni driver can allocate DMA descriptors. Failure to do
> this leads to faults when using devices such as an i2c touchscreen where
> the transaction is large
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