On Monday 08 September 2014 11:52:47 Murali Karicheri wrote:
> On 09/05/2014 05:11 PM, Arnd Bergmann wrote:
> > But the driver can only do root complex mode, and we would probably
> > want a completely different driver if we were to start supporting
> > endpoint mode.
>
> Good point! I will drop i
On 09/05/2014 05:11 PM, Arnd Bergmann wrote:
On Friday 05 September 2014 16:37:25 Murali Karicheri wrote:
On 09/05/2014 03:00 PM, Arnd Bergmann wrote:
On Friday 05 September 2014 14:33:54 Murali Karicheri wrote:
This looks like it's a shared register of some sort that doesn't
really belong int
On Friday 05 September 2014 16:37:25 Murali Karicheri wrote:
> On 09/05/2014 03:00 PM, Arnd Bergmann wrote:
> > On Friday 05 September 2014 14:33:54 Murali Karicheri wrote:
> >>> This looks like it's a shared register of some sort that doesn't
> >>> really belong into the registers of a particular
On 09/05/2014 03:00 PM, Arnd Bergmann wrote:
On Friday 05 September 2014 14:33:54 Murali Karicheri wrote:
This looks like it's a shared register of some sort that doesn't
really belong into the registers of a particular port. Could it
be that it's actually for the PHY?
This a shared device con
On Friday 05 September 2014 14:33:54 Murali Karicheri wrote:
> > This looks like it's a shared register of some sort that doesn't
> > really belong into the registers of a particular port. Could it
> > be that it's actually for the PHY?
> >
> This a shared device configuration register between the
On 09/05/2014 01:54 PM, Arnd Bergmann wrote:
On Friday 05 September 2014 13:39:42 Murali Karicheri wrote:
+
/* enable RC mode in devcfg */
val = readl(reg_p);
- val&= ~PCIE_MODE_MASK;
- val |= PCIE_RC_MODE;
+ port_id<<= 1;
+ val&= ~(PCIE_MODE_MASK<< por
On Friday 05 September 2014 13:39:42 Murali Karicheri wrote:
> +
> /* enable RC mode in devcfg */
> val = readl(reg_p);
> - val &= ~PCIE_MODE_MASK;
> - val |= PCIE_RC_MODE;
> + port_id <<= 1;
> + val &= ~(PCIE_MODE_MASK << port_id);
> + val |= (PCIE_RC_
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