Hi again Sören,
> Sounds good. AFAICT, the change below should be OK. Probably some
> stylistic changes to make it blend in with the rest of the DT (e.g.
> use lower case characters in the address parts of the node name).
The change to low characters has been made for address part. I also
delete
Hi Muhammad,
On Mon, 2016-10-03 at 14:56:16 +0200, Muhammad Abdul WAHAB wrote:
> Hi Sören,
>
> > I tried to refresh my Zynq knowledge a bit. The clkc provides the
> > dbg_trc clock, and that is the clock you need (not fclk). I couldn't
> > find it in the binding (I guess I messed that up), but ap
Hi Sören,
> I tried to refresh my Zynq knowledge a bit. The clkc provides the
> dbg_trc clock, and that is the clock you need (not fclk). I couldn't
> find it in the binding (I guess I messed that up), but apparently,
> you can provide a 'trace_emio_clk' as input to the clkc node in the
> Zynq DT
Hi Muhammad,
On Fri, 2016-09-30 at 09:39:51 +0200, Muhammad Abdul WAHAB wrote:
> Hi Sören,
>
> Thank you for your remarks. I corrected a few things as you suggested.
>
[...]
> >> +tpiu@F8803000 {
> >>>
> >>> +compatible = "arm,coresight-tpiu", "arm,primecell";
> >>> +
Hi Sören,
Thank you for your remarks. I corrected a few things as you suggested.
> I'm curious, did you test that with external debug tools. I have the
> feeling the kernel using the debug HW could interfere with JTAG
> debuggers, external trace tools, etc.
I did not test with any external debu
Hi Muhammad,
On Thu, 2016-09-29 at 12:26:13 +0200, Muhammad Abdul WAHAB wrote:
> The Coresight components are present on the Zynq SoC but the corresponding
> device tree entries are missing. This patch adds device tree entries for
> coresight components while explaining how it was done in order to
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