> On Jul 2, 2015, at 11:49 AM, Luis R. Rodriguez wrote:
>
> On Sat, Jun 27, 2015 at 08:00:48AM +1000, Benjamin Herrenschmidt wrote:
>> On Fri, 2015-06-26 at 16:24 +, Casey Leedom wrote:
>>> Thanks for looking into this Ben. As it stands now, it seems as
>>> if Write Combined mappings simpl
On Thu, 2015-07-02 at 20:49 +0200, Luis R. Rodriguez wrote:
> > The question then is what is "the right thing". In the powerpc case,
> > we'll have a non-garded mapping, which means we also get no ordering
> > between load and stores.
>
> I don't follow, you *ordering* between load and stores for
On Sat, Jun 27, 2015 at 08:00:48AM +1000, Benjamin Herrenschmidt wrote:
> On Fri, 2015-06-26 at 16:24 +, Casey Leedom wrote:
> > Thanks for looking into this Ben. As it stands now, it seems as
> > if Write Combined mappings simply aren't supported and/or all
> > driver writers trying to util
On Fri, 2015-06-26 at 21:31 +0200, Luis R. Rodriguez wrote:
> > Yeah either, we need to fix our relaxed implementation (patch
> > welcome :-)
>
> Yikes, so although powerpc has useful heuristics to automatically
> enable WC the default write ops have been nullifying its effects?
The heuristic is
ev; Suresh Siddha; Ingo Molnar;
> Thomas Gleixner; Daniel Vetter; Dave Airlie; Antonino Daplas; Jean-Christophe
> Plagniol-Villard; Dave Hansen; venkatesh.pallip...@intel.com; Stefan Bader;
> ville.syrj...@linux.intel.com; David Vrabel; Jan Beulich; Roger Pau Monné
> Subject: Re: [PATCH v7 5/9] PCI
On Fri, Jun 26, 2015 at 08:51:58AM +1000, Benjamin Herrenschmidt wrote:
> On Thu, 2015-06-25 at 21:40 +, Casey Leedom wrote:
> > Hhmmm, so what do PowerPC Drivers do when they want to take
> > advantage of Write Combining? Do their own Endian Swizzling
> > with the __raw_*() APIs?
>
> Yeah ei
hristophe
Plagniol-Villard; Dave Hansen; venkatesh.pallip...@intel.com; Stefan Bader;
ville.syrj...@linux.intel.com; David Vrabel; Jan Beulich; Roger Pau Monné
Subject: Re: [PATCH v7 5/9] PCI: Add pci_iomap_wc() variants
On Thu, 2015-06-25 at 21:40 +, Casey Leedom wrote:
>
> Ah, thank
On Thu, 2015-06-25 at 21:40 +, Casey Leedom wrote:
>
> Ah, thanks. I see now that the __raw_*() APIs don't do any of the
> Endian Swizzling. Unfortunately the *_relaxed() APIs on PowerPC
> are just defined as the normal *() routines. From
> arch/powerpc/include/asm/io.h:
>
> /*
>
On Thu, 2015-06-25 at 21:40 +, Casey Leedom wrote:
> Hhmmm, so what do PowerPC Drivers do when they want to take
> advantage of Write Combining? Do their own Endian Swizzling
> with the __raw_*() APIs?
Yeah either, we need to fix our relaxed implementation (patch
welcome :-)
Cheers,
Ben.
-
| From: Arnd Bergmann [a...@arndb.de]
| Sent: Thursday, June 25, 2015 1:44 PM
|
| On Thursday 25 June 2015 15:01:56 Casey Leedom wrote:
| >
| > Is there a reference I can read on this so I can understand
| > when and where we can use the __raw_*() APIs? Can these
| > Raw Read/Write operations b
On Thursday 25 June 2015 15:01:56 Casey Leedom wrote:
>
> Is there a reference I can read on this so I can understand
> when and where we can use the __raw_*() APIs? Can these
> Raw Read/Write operations be reordered with respect to
> each other or are the use of the various flavors of SYNC
> i
/ From: Benjamin Herrenschmidt [b...@kernel.crashing.org]
| Sent: Wednesday, June 24, 2015 4:38 PM
|
| It is to be noted that on powerpc at least, writel() and co will never
| combine due to the memory barriers in them. Only "normal" stores (or
\ __raw_writel) will.
/ From: Benjamin Herrenschmidt
On Wed, 2015-06-24 at 18:38 +0200, Luis R. Rodriguez wrote:
> On Wed, Jun 24, 2015 at 08:42:23AM +1000, Benjamin Herrenschmidt wrote:
> > On Fri, 2015-06-19 at 15:08 -0700, Luis R. Rodriguez wrote:
> > > From: "Luis R. Rodriguez"
> > >
> > > PCI BARs tell us whether prefetching is safe, but they
On Thu, 2015-06-25 at 02:08 +0200, Luis R. Rodriguez wrote:
>
> OK thanks I'll proceed with these patches then.
>
> > As for user mappings,
>
> Which APIs were you considering in this regard BTW?
mmap of the generic /sys/bus/pci/.../resource*
> > maybe the right thing to do is to let us do wha
On Thu, Jun 25, 2015 at 09:38:01AM +1000, Benjamin Herrenschmidt wrote:
> On Wed, 2015-06-24 at 15:29 -0700, Luis R. Rodriguez wrote:
>
> > Nope but at least what made me squint at this being a possible
> > "feature" was that in practice when reviewing all of the kernels
> > pending device drivers
On Wed, 2015-06-24 at 15:29 -0700, Luis R. Rodriguez wrote:
> Nope but at least what made me squint at this being a possible
> "feature" was that in practice when reviewing all of the kernels
> pending device drivers using MTRR (potential write-combine candidates)
> I encountered a slew of them wh
On Wed, Jun 24, 2015 at 3:05 PM, Benjamin Herrenschmidt
wrote:
> On Wed, 2015-06-24 at 18:38 +0200, Luis R. Rodriguez wrote:
>> On Wed, Jun 24, 2015 at 08:42:23AM +1000, Benjamin Herrenschmidt wrote:
>> > On Fri, 2015-06-19 at 15:08 -0700, Luis R. Rodriguez wrote:
>> > > From: "Luis R. Rodriguez"
On Wed, Jun 24, 2015 at 08:42:23AM +1000, Benjamin Herrenschmidt wrote:
> On Fri, 2015-06-19 at 15:08 -0700, Luis R. Rodriguez wrote:
> > From: "Luis R. Rodriguez"
> >
> > PCI BARs tell us whether prefetching is safe, but they don't say anything
> > about write combining (WC). WC changes orderin
On Fri, 2015-06-19 at 15:08 -0700, Luis R. Rodriguez wrote:
> From: "Luis R. Rodriguez"
>
> PCI BARs tell us whether prefetching is safe, but they don't say anything
> about write combining (WC). WC changes ordering rules and allows writes to
> be collapsed, so it's not safe in general to use it
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