Hi Han,
On 03.12.18 21:54, Han Xu wrote:
[...]
>>>
>>> Hi Schrempf, I am reviewing and testing on some i.MX platforms, please
>> hold on for a while for the result.
>>
>> Okay, thanks! I'm looking forward to see the results.
>
> Hi Schrempf, I am good with the patch set(with warning fix) and it w
Cc: dw...@infradead.org; computersforpe...@gmail.com;
> rich...@nod.at; miquel.ray...@bootlin.com; David Wolfe
> ; Fabio Estevam ;
> Prabhakar Kushwaha ;
> shawn...@kernel.org; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v6 3/9] spi: Add a driver for the Freescale/NXP QuadSPI
> controlle
od.at;
> >> miquel.ray...@bootlin.com; David Wolfe ; Fabio
> >> Estevam ; Prabhakar Kushwaha
> >> ; Yogesh Narayan Gaur
> >> ; shawn...@kernel.org; linux-
> >> ker...@vger.kernel.org
> >> Subject: Re: [PATCH v6 3/9] spi: Add a driver for the Freescale/NXP
gt; Brown ; Han Xu
>>>> Cc: dw...@infradead.org; computersforpe...@gmail.com;
>> rich...@nod.at;
>>>> miquel.ray...@bootlin.com; David Wolfe ; Fabio
>>>> Estevam ; Prabhakar Kushwaha
>>>> ; Yogesh Narayan Gaur
>>>> ; shawn...@kernel.org;
Cc: dw...@infradead.org; computersforpe...@gmail.com;
> rich...@nod.at; miquel.ray...@bootlin.com; David Wolfe
> ; Fabio Estevam ;
> Prabhakar Kushwaha ;
> shawn...@kernel.org; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v6 3/9] spi: Add a driver for the Freescale/NXP QuadSPI
> control
an Gaur
>> ; shawn...@kernel.org; linux-
>> ker...@vger.kernel.org
>> Subject: Re: [PATCH v6 3/9] spi: Add a driver for the Freescale/NXP QuadSPI
>> controller
>>
>> On 27.11.18 11:24, Schrempf Frieder wrote:
>>> This driver is derived from the SPI NOR driver
; Han Xu
> Cc: dw...@infradead.org; computersforpe...@gmail.com; rich...@nod.at;
> miquel.ray...@bootlin.com; David Wolfe ; Fabio
> Estevam ; Prabhakar Kushwaha
> ; Yogesh Narayan Gaur
> ; shawn...@kernel.org; linux-
> ker...@vger.kernel.org
> Subject: Re: [PATCH v6 3/9] spi: Add
On 27.11.18 11:24, Schrempf Frieder wrote:
> This driver is derived from the SPI NOR driver at
> mtd/spi-nor/fsl-quadspi.c. It uses the new SPI memory interface
> of the SPI framework to issue flash memory operations to up to
> four connected flash chips (2 buses with 2 CS each).
>
> The controlle
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