> I want to see how my code bahaves during rare (?) events: an overflow of
> the RX fifo (256 bytes) and a TX underrun. It's my understanding that if the
> adapter pains at DMAing, those errors should be triggered.
> Could I/O at a inocuous location (a well-choosen PCI register ?) be enough
> f
Hello,
Context:
HDLC PCI adapter + line at 2 Mb/s + external traffic generator that fills
the line with 5 to x1000 bytes frame.
I want to see how my code bahaves during rare (?) events: an overflow of
the RX fifo (256 bytes) and a TX underrun. It's my understanding that if the
adapter pains a
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