On Wed, Jun 26, 2019 at 08:48:37AM +0200, Christoph Hellwig wrote:
> On Tue, Jun 25, 2019 at 09:37:22AM -0700, Mark Greer wrote:
> > Yeah, the mpsc driver had lots of ugly cache related hacks because of
> > cache coherency bugs in the early version of the MV64x60 bridge chips
> > that it was embedd
On Tue, Jun 25, 2019 at 09:37:22AM -0700, Mark Greer wrote:
> Yeah, the mpsc driver had lots of ugly cache related hacks because of
> cache coherency bugs in the early version of the MV64x60 bridge chips
> that it was embedded in. That chip is pretty much dead now and I've
> removed core support f
On Tue, Jun 25, 2019 at 02:26:41PM +0200, Christoph Hellwig wrote:
> Hi Paul, Dale and Mark (I hope this reaches the right Mark),
Hi Christoph. Yes, you did reach the right Mark. :)
> I've started auditing all users of DMA_ATTR_NON_CONSISTENT ot prepare
> for major API improvements in that area
Hi Paul, Dale and Mark (I hope this reaches the right Mark),
I've started auditing all users of DMA_ATTR_NON_CONSISTENT ot prepare
for major API improvements in that area.
One of the odd users is the mpsc ัerial driver, which allocates DMA
memory with the above flag, and then actually properly ca
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