Eric W. Biederman wrote:
"Jeff V. Merkey" <[EMAIL PROTECTED]> writes:
Eric,
Please find attached the APIC code I used in Gadugi. It's code for plain vanilla
APICs, but does just this. This code not only allows
interrupts to be migrated, but processors to be stopped and restarted on the fly
"Jeff V. Merkey" <[EMAIL PROTECTED]> writes:
> Eric,
>
> Please find attached the APIC code I used in Gadugi. It's code for plain
> vanilla
> APICs, but does just this. This code not only allows
> interrupts to be migrated, but processors to be stopped and restarted on the
> fly
> without system
Eric,
Please find attached the APIC code I used in Gadugi. It's code for plain
vanilla APICs, but does just this. This code not only allows
interrupts to be migrated, but processors to be stopped and restarted on
the fly without system interruption. You may find some useful
ideas in it.
Jeff
Here's the include file that goes with it.
Jeff
#include "types.h"
#include "emit.h"
#define _82489APIC_MASK 0x00F0
#define APIC_IO_REG 0x
#define APIC_IO_DATA 0x0004
// APIC registers are 128 bit aligned. accesses are offset * 4
#define APIC_TASKPRI (4 * 0x0008)
#define
"Jeff V. Merkey" <[EMAIL PROTECTED]> writes:
> In my older days of programmin 82489DX chipsets (which the AMD APIC versions
> resemble
> the 82489DX more closely than intel's newer incarnations), you had to EOI the
> apic early if you
> wanted to migrate interrupt assignments. I had to do the foll
Eric W. Biederman wrote:
** Conclusions.
*IRQs must be reprogramed in interrupt context.
The result of this is investigation is that I am convinced we need
to perform the irq migration activities in interrupt context although
I am not convinced it is completely safe. I suspect multiple irqs
Ok. This is just an email to summarize my findings after investigating
the ioapic programming.
The ioapics on the E75xx chipset do have issues if you attempt to
reprogramming them outside of the irq handler. I have on several
instances caused the state machine to get stuck such that an
individua
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