On Tue 2014-07-08 13:54:58, Borislav Petkov wrote:
> On Tue, Jul 08, 2014 at 01:52:05PM +0200, Pavel Machek wrote:
> > I'm not joking. Try to understand and verify the code above. You
> > can't. The "descriptive macro names" are useless; all the code does is
> > split register in pieces. With the n
On Tue, Jul 08, 2014 at 01:52:05PM +0200, Pavel Machek wrote:
> I'm not joking. Try to understand and verify the code above. You
> can't. The "descriptive macro names" are useless; all the code does is
> split register in pieces. With the numbers it would be very obvious.
No, you need to fix the
On Tue 2014-07-08 13:42:28, Borislav Petkov wrote:
> On Tue, Jul 08, 2014 at 01:31:09PM +0200, Pavel Machek wrote:
> > > + read_reg = readl(mc_vbase + DRAMADDRW);
> > > +
> > > + width = readl(mc_vbase + DRAMIFWIDTH);
> > > +
> > > + col = (read_reg & DRAMADDRW_COLBIT_MASK) >>
> > > + DRAMA
On Tue, Jul 08, 2014 at 01:31:09PM +0200, Pavel Machek wrote:
> > + read_reg = readl(mc_vbase + DRAMADDRW);
> > +
> > + width = readl(mc_vbase + DRAMIFWIDTH);
> > +
> > + col = (read_reg & DRAMADDRW_COLBIT_MASK) >>
> > + DRAMADDRW_COLBIT_LSB;
> > + row = (read_reg & DRAMADDRW_ROWB
> + read_reg = readl(mc_vbase + DRAMADDRW);
> +
> + width = readl(mc_vbase + DRAMIFWIDTH);
> +
> + col = (read_reg & DRAMADDRW_COLBIT_MASK) >>
> + DRAMADDRW_COLBIT_LSB;
> + row = (read_reg & DRAMADDRW_ROWBIT_MASK) >>
> + DRAMADDRW_ROWBIT_LSB;
> + bank = (
Hi Dinh,
On Wed, Jun 25, 2014 at 4:12 PM, Dinh Nguyen wrote:
> Hi Thor,
>
>
> On 06/25/2014 04:15 PM, ttha...@altera.com wrote:
>>
>> From: Thor Thayer
>>
>> This patch adds support for the CycloneV and ArriaV SDRAM controllers.
>> Correction and reporting of SBEs, Panic on DBEs.
>>
>> Signed-of
Hi Thor,
On 06/25/2014 04:15 PM, ttha...@altera.com wrote:
From: Thor Thayer
This patch adds support for the CycloneV and ArriaV SDRAM controllers.
Correction and reporting of SBEs, Panic on DBEs.
Signed-off-by: Thor Thayer
---
v2: Use the SDRAM controller registers to calculate memory size
From: Thor Thayer
This patch adds support for the CycloneV and ArriaV SDRAM controllers.
Correction and reporting of SBEs, Panic on DBEs.
Signed-off-by: Thor Thayer
---
v2: Use the SDRAM controller registers to calculate memory size
instead of the Device Tree. Update To & Cc list. Add main
On Mon, May 26, 2014 at 4:57 AM, Borislav Petkov wrote:
> On Thu, May 15, 2014 at 11:04:51AM -0500, ttha...@altera.com wrote:
>> From: Thor Thayer
>>
>> v2: Use the SDRAM controller registers to calculate memory size
>> instead of the Device Tree. Update To & Cc list. Add maintainer
>> in
On Thu, May 15, 2014 at 11:04:51AM -0500, ttha...@altera.com wrote:
> From: Thor Thayer
>
> v2: Use the SDRAM controller registers to calculate memory size
> instead of the Device Tree. Update To & Cc list. Add maintainer
> information.
>
> v3: EDAC driver cleanup based on comments from
From: Thor Thayer
v2: Use the SDRAM controller registers to calculate memory size
instead of the Device Tree. Update To & Cc list. Add maintainer
information.
v3: EDAC driver cleanup based on comments from Mailing list.
v4: Panic on DBE. Add macro around inject-error reads to prevent
[PATCHv5 1/3] dts: socfpga: Add bindings for Altera SoC SDRAM
[PATCHv5 2/3] dts: socfpga: Add bindings for Altera SoC SDRAM EDAC
[PATCHv5 3/3] edac: altera: Add EDAC support for Altera SoC SDRAM
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On Mon, May 12, 2014 at 7:12 PM, Borislav Petkov wrote:
> On Mon, May 12, 2014 at 06:36:57PM -0500, ttha...@altera.com wrote:
>> + ptemp[0] = 0x5A5A5A5A;
>> + ptemp[1] = 0xA5A5A5A5;
>> + /* Clear the error injection bits */
>> + regmap_write(drvdata->mc_vbase, CTLCFG, read_reg);
>>
On Mon, May 12, 2014 at 06:36:57PM -0500, ttha...@altera.com wrote:
> + ptemp[0] = 0x5A5A5A5A;
> + ptemp[1] = 0xA5A5A5A5;
> + /* Clear the error injection bits */
> + regmap_write(drvdata->mc_vbase, CTLCFG, read_reg);
> + /* Ensure it has been written out */
> + wmb();
> +
>
From: Thor Thayer
This patch adds EDAC support for reporting ECC errors of CycloneV
and ArriaV SDRAM controllers.
- The SDRAM Controller registers are shared with the FPGA bridge so
these are accessed through the syscon interface.
- The configuration of the SDRAM memory size for the EDAC
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