On Fri, Oct 16, 2020 at 4:09 PM Mel Gorman wrote:
>
> On Fri, Oct 16, 2020 at 03:41:12PM +0200, Rafael J. Wysocki wrote:
> > > Turns out I didn't even have that. On another machine (same model,
> > > same cpu, different BIOS that cannot be updated), enabling the C6 state
> > > still did not enable
On Fri, Oct 16, 2020 at 03:41:12PM +0200, Rafael J. Wysocki wrote:
> > Turns out I didn't even have that. On another machine (same model,
> > same cpu, different BIOS that cannot be updated), enabling the C6 state
> > still did not enable it on boot and dmesg complained about CST not being
> > usab
On Thu, Oct 15, 2020 at 8:34 PM Mel Gorman wrote:
>
> > Yes, it's well hidden but it's there. If the profile is made custom, then
> > the p-states can be selected and "custom" default enables C6 but not C3
> > (there is a note saying that it's not recommended for that CPU). If I
> > then switch it
> Yes, it's well hidden but it's there. If the profile is made custom, then
> the p-states can be selected and "custom" default enables C6 but not C3
> (there is a note saying that it's not recommended for that CPU). If I
> then switch it back to the normal profile, the c-states are not restored
>
On Tue, Oct 13, 2020 at 08:55:26PM +0200, Rafael J. Wysocki wrote:
> > > With C6 enabled, that state is used at
> > > least sometimes (so C1E is used less often), but PC6 doesn't seem to be
> > > really used - it looks like core C6 only is entered and which may be why
> > > C6
> > > adds less late
On 10/8/2020 7:34 PM, Mel Gorman wrote:
On Thu, Oct 08, 2020 at 07:15:46PM +0200, Rafael J. Wysocki wrote:
Force enabling C6
./5.9.0-rc8-enable-c6/iter-0/sys/devices/system/cpu/cpu0/cpuidle/state0/disable:0
./5.9.0-rc8-enable-c6/iter-0/sys/devices/system/cpu/cpu0/cpuidle/state1/disable:0
./5.9.
On Thu, Oct 08, 2020 at 07:15:46PM +0200, Rafael J. Wysocki wrote:
> > Force enabling C6
> >
> > ./5.9.0-rc8-enable-c6/iter-0/sys/devices/system/cpu/cpu0/cpuidle/state0/disable:0
> > ./5.9.0-rc8-enable-c6/iter-0/sys/devices/system/cpu/cpu0/cpuidle/state1/disable:0
> > ./5.9.0-rc8-enable-c6/iter-0/
On 10/8/2020 11:09 AM, Mel Gorman wrote:
On Wed, Oct 07, 2020 at 05:45:30PM +0200, Rafael J. Wysocki wrote:
pre-cst is just before your patch
enable-cst is your patch that was bisected
enable-cst-no-hsx-acpi is your patch with use_acpi disabled
5.9-rc8-vanilla is what it sounds like
5.9-rc8-no-h
On Wed, Oct 07, 2020 at 05:45:30PM +0200, Rafael J. Wysocki wrote:
> > pre-cst is just before your patch
> > enable-cst is your patch that was bisected
> > enable-cst-no-hsx-acpi is your patch with use_acpi disabled
> > 5.9-rc8-vanilla is what it sounds like
> > 5.9-rc8-no-hsx-acpi disables use_acp
On Wed, Oct 07, 2020 at 05:40:43PM +0200, Rafael J. Wysocki wrote:
> > # grep . enable-cst/cpuidle/state*/disable
> > enable-cst/cpuidle/state0/disable:0
> > enable-cst/cpuidle/state1/disable:0
> > enable-cst/cpuidle/state2/disable:0
> > enable-cst/cpuidle/state3/disable:1
> > enable-cst/cpuidle/st
On 10/6/2020 11:18 PM, Mel Gorman wrote:
On Tue, Oct 06, 2020 at 09:29:24PM +0200, Rafael J. Wysocki wrote:
After the commit, the default_status file does not appear in /sys
Something is amiss, then, because the commit doesn't affect the presence of
this file.
This was cleared up in another
On 10/6/2020 9:47 PM, Mel Gorman wrote:
On Tue, Oct 06, 2020 at 08:03:22PM +0100, Mel Gorman wrote:
On Tue, Oct 06, 2020 at 06:00:18PM +0200, Rafael J. Wysocki wrote:
server systems") and enable-cst is the commit. It was not fixed by 5.6 or
5.9-rc8. A lot of bisections ended up here including k
On Tue, Oct 06, 2020 at 09:29:24PM +0200, Rafael J. Wysocki wrote:
> > After the commit, the default_status file does not appear in /sys
> >
> Something is amiss, then, because the commit doesn't affect the presence of
> this file.
>
This was cleared up in another mail.
> The only thing it does
On Tue, Oct 06, 2020 at 08:03:22PM +0100, Mel Gorman wrote:
> On Tue, Oct 06, 2020 at 06:00:18PM +0200, Rafael J. Wysocki wrote:
> > > server systems") and enable-cst is the commit. It was not fixed by 5.6 or
> > > 5.9-rc8. A lot of bisections ended up here including kernel compilation,
> > > tbenc
On 10/6/2020 9:03 PM, Mel Gorman wrote:
On Tue, Oct 06, 2020 at 06:00:18PM +0200, Rafael J. Wysocki wrote:
server systems") and enable-cst is the commit. It was not fixed by 5.6 or
5.9-rc8. A lot of bisections ended up here including kernel compilation,
tbench, syscall entry/exit microbenchmark,
On Tue, Oct 06, 2020 at 06:00:18PM +0200, Rafael J. Wysocki wrote:
> > server systems") and enable-cst is the commit. It was not fixed by 5.6 or
> > 5.9-rc8. A lot of bisections ended up here including kernel compilation,
> > tbench, syscall entry/exit microbenchmark, hackbench, Java workloads etc.
Hi Mel,
On 10/6/2020 10:36 AM, Mel Gorman wrote:
Hi Rafael,
Numerous workload regressions have bisected repeatedly to the commit
6d4f08a6776 ("intel_idle: Use ACPI _CST on server systems") but only on
a set of haswell machines that all have the same CPU.
CPU(s): 48
On-line CPU(s)
Hi Rafael,
Numerous workload regressions have bisected repeatedly to the commit
6d4f08a6776 ("intel_idle: Use ACPI _CST on server systems") but only on
a set of haswell machines that all have the same CPU.
CPU(s): 48
On-line CPU(s) list: 0-47
Thread(s) per core: 2
Core(s) per socket
18 matches
Mail list logo
