Hi,
* Li, Tong N ([EMAIL PROTECTED]) wrote:
> Mathieu,
>
> > cycles_per_iter = 0.0;
> > for (i=0; i > time1 = get_cycles();
> > for (j = 0; j < NR_ITER; j++) {
> > testval = &array[random() % ARRAY_SIZE];
> > }
> > time2
Mathieu,
> cycles_per_iter = 0.0;
> for (i=0; i time1 = get_cycles();
> for (j = 0; j < NR_ITER; j++) {
> testval = &array[random() % ARRAY_SIZE];
> }
> time2 = get_cycles();
> cycles_per_iter +
* Li, Tong N ([EMAIL PROTECTED]) wrote:
> > Also cache misses in this situation tend to be much more than 48
> cycles
> > (even an K8 with integrated memory controller with fastest DIMMs is
> > slower than that) Mathieu probably measured an L2 miss, not a load
> from
> > RAM.
> > Load from RAM can
3 matches
Mail list logo