On Mon, 1 Oct 2018, Yasha Cherikovsky wrote:
> The Lexra LX5280 CPU [1][2] implements the MIPS-I ISA,
> without unaligned load/store instructions (lwl, lwr, swl, swr).
I think you actually need to emulate these missing instructions for user
programs, so that the 32-bit MIPS psABI is supported a
The Lexra LX5280 CPU [1][2] implements the MIPS-I ISA,
without unaligned load/store instructions (lwl, lwr, swl, swr).
The programming model of this CPU is very similar
to the R3000 programming model, with a few differences.
The Realtek RTL8186 SoC has this CPU, so this patch is required
for futur
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