On Sat, Sep 29, 2018 at 7:15 AM Palmer Dabbelt wrote:
>
> On Mon, 10 Sep 2018 06:34:18 PDT (-0700), Christoph Hellwig wrote:
> > On Thu, Sep 06, 2018 at 04:15:14PM +0530, Anup Patel wrote:
> >> This patch is doing two things:
> >> 1. Allow IRQCHIP driver to provide IPI trigger mechanism
> >
> > An
On Mon, 10 Sep 2018 06:34:18 PDT (-0700), Christoph Hellwig wrote:
On Thu, Sep 06, 2018 at 04:15:14PM +0530, Anup Patel wrote:
This patch is doing two things:
1. Allow IRQCHIP driver to provide IPI trigger mechanism
And the big questions is why do we want that? The last thing we
want is for p
On Mon, Sep 10, 2018 at 7:04 PM, Christoph Hellwig wrote:
> On Thu, Sep 06, 2018 at 04:15:14PM +0530, Anup Patel wrote:
>> This patch is doing two things:
>> 1. Allow IRQCHIP driver to provide IPI trigger mechanism
>
> And the big questions is why do we want that? The last thing we
> want is for
On Thu, Sep 06, 2018 at 04:15:14PM +0530, Anup Patel wrote:
> This patch is doing two things:
> 1. Allow IRQCHIP driver to provide IPI trigger mechanism
And the big questions is why do we want that? The last thing we
want is for people to "innovate" on how they deliver IPIs. RISC-V
has defined a
On Thu, Sep 6, 2018 at 3:15 PM, Palmer Dabbelt wrote:
> On Tue, 04 Sep 2018 11:50:02 PDT (-0700), Christoph Hellwig wrote:
>>
>> On Tue, Sep 04, 2018 at 06:15:10PM +0530, Anup Patel wrote:
>>>
>>> The mechanism to trigger IPI is generally part of interrupt-controller
>>> driver for various archite
On Tue, 04 Sep 2018 11:50:02 PDT (-0700), Christoph Hellwig wrote:
On Tue, Sep 04, 2018 at 06:15:10PM +0530, Anup Patel wrote:
The mechanism to trigger IPI is generally part of interrupt-controller
driver for various architectures. On RISC-V, we have an option to trigger
IPI using SBI or SOC ven
On Wed, Sep 05, 2018 at 10:06:24AM +0530, Anup Patel wrote:
> It's outrageous to call IPI mechanisms using interrupt-controller as "wacky".
I call pluggable IPI whacky, and it's not outragous. What is outragous
is your bullshit architecture astronaut patches.
There might be a nned to abstract IP
On Wed, Sep 5, 2018 at 12:20 AM, Christoph Hellwig wrote:
> On Tue, Sep 04, 2018 at 06:15:10PM +0530, Anup Patel wrote:
>> The mechanism to trigger IPI is generally part of interrupt-controller
>> driver for various architectures. On RISC-V, we have an option to trigger
>> IPI using SBI or SOC ven
On Tue, Sep 04, 2018 at 06:15:10PM +0530, Anup Patel wrote:
> The mechanism to trigger IPI is generally part of interrupt-controller
> driver for various architectures. On RISC-V, we have an option to trigger
> IPI using SBI or SOC vendor can implement RISC-V CPU where IPI will be
> triggered using
The mechanism to trigger IPI is generally part of interrupt-controller
driver for various architectures. On RISC-V, we have an option to trigger
IPI using SBI or SOC vendor can implement RISC-V CPU where IPI will be
triggered using SOC interrupt-controller (e.g. custom PLIC).
This patch makes IPI
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